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Searched refs:urb_gen5 (Results 1 – 3 of 3) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_eu_emit.c492 insn->bits3.urb_gen5.opcode = 1; /* FF_SYNC */ in brw_set_ff_sync_message()
493 insn->bits3.urb_gen5.offset = 0; /* Not used by FF_SYNC */ in brw_set_ff_sync_message()
494 insn->bits3.urb_gen5.swizzle_control = 0; /* Not used by FF_SYNC */ in brw_set_ff_sync_message()
495 insn->bits3.urb_gen5.allocate = allocate; in brw_set_ff_sync_message()
496 insn->bits3.urb_gen5.used = 0; /* Not used by FF_SYNC */ in brw_set_ff_sync_message()
497 insn->bits3.urb_gen5.complete = 0; /* Not used by FF_SYNC */ in brw_set_ff_sync_message()
525 insn->bits3.urb_gen5.opcode = 0; /* URB_WRITE */ in brw_set_urb_message()
526 insn->bits3.urb_gen5.offset = offset; in brw_set_urb_message()
527 insn->bits3.urb_gen5.swizzle_control = swizzle_control; in brw_set_urb_message()
528 insn->bits3.urb_gen5.allocate = allocate; in brw_set_urb_message()
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Dbrw_disasm.c1261 format (file, " %d", inst->bits3.urb_gen5.offset); in brw_disasm()
1269 inst->bits3.urb_gen5.opcode, &space); in brw_disasm()
Dbrw_structs.h1369 } urb_gen5; member