| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-subvector-extend.ll | 11 ; CHECK-NEXT: ushll.8h v0, v0, #0
28 ; CHECK-NEXT: ushll.8h v0, v0, #0
49 ; CHECK-NEXT: ushll.4s v0, v0, #0
66 ; CHECK-NEXT: ushll.4s v0, v0, #0
83 ; CHECK-NEXT: ushll.8h v0, v0, #0
85 ; CHECK-NEXT: ushll.4s v0, v0, #0
108 ; CHECK-NEXT: ushll.2d v0, v0, #0
125 ; CHECK-NEXT: ushll.4s v0, v0, #0
127 ; CHECK-NEXT: ushll.2d v0, v0, #0
|
| D | neon-shift-left-long.ll | 29 ; CHECK: ushll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #3
37 ; CHECK: ushll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #9
45 ; CHECK: ushll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #19
128 ; CHECK: ushll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0
135 ; CHECK: ushll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #0
142 ; CHECK: ushll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #0
198 ; CHECK-NEXT: ushll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0
|
| D | complex-int-to-fp.ll | 24 ; CHECK: ushll.2d [[VAL64:v[0-9]+]], v0, #0
45 ; CHECK: ushll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
66 ; CHECK: ushll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
139 ; CHECK: ushll.4s [[VAL32:v[0-9]+]], v0, #0
159 ; CHECK: ushll.4s [[VAL32:v[0-9]+]], v0, #0
|
| D | arm64-vbitwise.ll | 32 ;CHECK: ushll.8h
48 ;CHECK: ushll.4s
64 ;CHECK: ushll.2d
|
| D | arm64-extend-int-to-fp.ll | 5 ; CHECK: ushll.4s v0, v0, #0
|
| D | arm64-vector-ext.ll | 4 ;CHECK: ushll.4s v0, v0, #0
|
| D | arm64-vselect.ll | 7 ; ushll.4s v0, v0, #0
|
| D | fp16-v8-instructions.ll | 311 ; CHECK-NEXT: ushll v[[REG1:[0-9]+]].8h, v0.8b, #0
313 ; CHECK-NEXT: ushll [[HI:v[0-9]+\.4s]], v[[REG1]].4h, #0
327 ; CHECK-NEXT: ushll [[HI:v[0-9]+\.4s]], v0.4h, #0
|
| D | fp16-v4-instructions.ll | 181 ; CHECK-NEXT: ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0
192 ; CHECK-NEXT: ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0
|
| D | arm64-vshift.ll | 1140 ;CHECK: ushll.8h v0, {{v[0-9]+}}, #1
1149 ;CHECK: ushll.4s v0, {{v[0-9]+}}, #1
1158 ;CHECK: ushll.2d v0, {{v[0-9]+}}, #1
|
| /external/llvm/test/MC/AArch64/ |
| D | neon-shift-left-long.s | 25 ushll v0.8h, v1.8b, #3
26 ushll v0.4s, v1.4h, #3
27 ushll v0.2d, v1.2s, #3
|
| D | arm64-aliases.s | 708 ; CHECK: ushll.8h v1, v2, #0
710 ; CHECK: ushll.8h v1, v2, #0
713 ; CHECK: ushll.4s v1, v2, #0
715 ; CHECK: ushll.4s v1, v2, #0
718 ; CHECK: ushll.2d v1, v2, #0
720 ; CHECK: ushll.2d v1, v2, #0
|
| D | arm64-advsimd.s | 1451 ushll.8h v0, v0, #1
1453 ushll.4s v0, v0, #3
1455 ushll.2d v0, v0, #5
1623 ; CHECK: ushll.8h v0, v0, #1 ; encoding: [0x00,0xa4,0x09,0x2f]
1625 ; CHECK: ushll.4s v0, v0, #3 ; encoding: [0x00,0xa4,0x13,0x2f]
1627 ; CHECK: ushll.2d v0, v0, #5 ; encoding: [0x00,0xa4,0x25,0x2f]
1713 ushll v13.8h, v6.8b, #3
1714 ushll v14.4s, v7.4h, #2
1715 ushll v15.2d, v8.2s, #7
1775 ; CHECK: ushll.8h v13, v6, #3 ; encoding: [0xcd,0xa4,0x0b,0x2f]
[all …]
|
| D | neon-diagnostics.s | 1327 ushll v1.16b, v25.16b, #6
1334 ushll v0.4s, v1.4h, #17
1335 ushll v0.2d, v1.2s, #33
|
| /external/libavc/common/armv8/ |
| D | ih264_deblk_luma_av8.s | 159 ushll v26.8h, v9.8b, #1 //
161 ushll v16.8h, v8.8b, #1 //Q13,Q8 = (p1<<1)
165 ushll v16.8h, v2.8b, #1 //
166 ushll v26.8h, v3.8b, #1 //Q13,Q8 = (q1<<1)
|
| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.c | 4358 GEN_SHIFT_TEST(ushll, 2d, 2s, 0)
4359 GEN_SHIFT_TEST(ushll, 2d, 2s, 15)
4360 GEN_SHIFT_TEST(ushll, 2d, 2s, 31)
4364 GEN_SHIFT_TEST(ushll, 4s, 4h, 0)
4365 GEN_SHIFT_TEST(ushll, 4s, 4h, 7)
4366 GEN_SHIFT_TEST(ushll, 4s, 4h, 15)
4370 GEN_SHIFT_TEST(ushll, 8h, 8b, 0)
4371 GEN_SHIFT_TEST(ushll, 8h, 8b, 3)
4372 GEN_SHIFT_TEST(ushll, 8h, 8b, 7)
|
| D | fp_and_simd.stdout.exp | 28686 ushll v8.2d, v7.2s, #0 8e39d5de8d87ec9802284a7210c8824a 0000000002284a720000000010c8824a fpsr=000…
28688 ushll v8.2d, v7.2s, #15 0dac5506e002e8697795fa0e7261107e 00003bcafd07000000003930883f0000 fpsr=00…
28689 ushll v8.2d, v7.2s, #31 3504ac137efffa47b15815576cdcf8f7 58ac0aab80000000366e7c7b80000000 fpsr=00…
28693 ushll v8.4s, v7.4h, #0 5d08e064d8b5896e46722b74385393c9 0000467200002b7400003853000093c9 fpsr=000…
28694 ushll v8.4s, v7.4h, #7 459ebe0c23be1b71512836c4e040d405 00289400001b620000702000006a0280 fpsr=000…
28695 ushll v8.4s, v7.4h, #15 9d01fc4001b2caa8eb1d366a687778ae 758e80001b350000343b80003c570000 fpsr=00…
28699 ushll v8.8h, v7.8b, #0 59431abc2b501fc7cb0d2e8a3cef51d0 00cb000d002e008a003c00ef005100d0 fpsr=000…
28700 ushll v8.8h, v7.8b, #3 5b6c87d21e5877eb1e7cc67fdaa07603 00f003e0063003f806d0050003b00018 fpsr=000…
28701 ushll v8.8h, v7.8b, #7 954bdb1decb2f46cc712db72a00406cc 638009006d8039005000020003006600 fpsr=000…
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 2177 # CHECK: ushll.8h v0, v0, #1
2179 # CHECK: ushll.4s v0, v0, #3
2181 # CHECK: ushll.2d v0, v0, #5
|
| /external/vixl/src/vixl/a64/ |
| D | simulator-a64.h | 2095 LogicVRegister ushll(VectorFormat vform,
|
| D | assembler-a64.cc | 4252 void Assembler::ushll(const VRegister& vd, in ushll() function in vixl::Assembler
4270 ushll(vd, vn, 0); in uxtl()
|
| D | macro-assembler-a64.h | 2401 V(ushll, Ushll) \
|
| D | assembler-a64.h | 2878 void ushll(const VRegister& vd,
|
| D | simulator-a64.cc | 3813 ushll(vf, rd, rn, left_shift); in VisitNEONShiftImmediate()
|
| /external/vixl/test/ |
| D | test-simulator-a64.cc | 3888 DEFINE_TEST_NEON_2OPIMM_LONG(ushll, Basic, TypeWidthFromZero) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
|
| /external/vixl/doc/ |
| D | supported-instructions.md | 4473 void ushll(const VRegister& vd,
|