| /external/llvm/test/MC/AArch64/ |
| D | neon-shift-left-long.s | 28 ushll2 v0.8h, v1.16b, #3
29 ushll2 v0.4s, v1.8h, #3
30 ushll2 v0.2d, v1.4s, #3
|
| D | arm64-aliases.s | 723 ; CHECK: ushll2.8h v1, v2, #0
725 ; CHECK: ushll2.8h v1, v2, #0
728 ; CHECK: ushll2.4s v1, v2, #0
730 ; CHECK: ushll2.4s v1, v2, #0
733 ; CHECK: ushll2.2d v1, v2, #0
735 ; CHECK: ushll2.2d v1, v2, #0
|
| D | arm64-advsimd.s | 1452 ushll2.8h v0, v0, #2
1454 ushll2.4s v0, v0, #4
1456 ushll2.2d v0, v0, #6
1624 ; CHECK: ushll2.8h v0, v0, #2 ; encoding: [0x00,0xa4,0x0a,0x6f]
1626 ; CHECK: ushll2.4s v0, v0, #4 ; encoding: [0x00,0xa4,0x14,0x6f]
1628 ; CHECK: ushll2.2d v0, v0, #6 ; encoding: [0x00,0xa4,0x26,0x6f]
1710 ushll2 v10.8h, v3.16b, #6
1711 ushll2 v11.4s, v4.8h, #5
1712 ushll2 v12.2d, v5.4s, #4
1772 ; CHECK: ushll2.8h v10, v3, #6 ; encoding: [0x6a,0xa4,0x0e,0x6f]
[all …]
|
| D | neon-diagnostics.s | 1329 ushll2 v1.4s, v25.4s, #7
1338 ushll2 v0.2d, v1.4s, #33
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-subvector-extend.ll | 27 ; CHECK-NEXT: ushll2.8h v1, v0, #0
65 ; CHECK-NEXT: ushll2.4s v1, v0, #0
84 ; CHECK-NEXT: ushll2.4s v1, v0, #0
107 ; CHECK-NEXT: ushll2.2d v1, v0, #0
126 ; CHECK-NEXT: ushll2.2d v1, v0, #0
|
| D | neon-shift-left-long.ll | 80 ; CHECK: ushll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #3
89 ; CHECK: ushll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #9
98 ; CHECK: ushll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #19
173 ; CHECK: ushll2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, #0
181 ; CHECK: ushll2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, #0
189 ; CHECK: ushll2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, #0
|
| D | fp16-v8-instructions.ll | 312 ; CHECK-NEXT: ushll2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h, #0
326 ; CHECK-NEXT: ushll2 [[LO:v[0-9]+\.4s]], v0.8h, #0
|
| D | arm64-vshift.ll | 1167 ;CHECK: ushll2.8h v0, {{v[0-9]+}}, #1
1177 ;CHECK: ushll2.4s v0, {{v[0-9]+}}, #1
1187 ;CHECK: ushll2.2d v0, {{v[0-9]+}}, #1
|
| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.c | 4361 GEN_SHIFT_TEST(ushll2, 2d, 4s, 0)
4362 GEN_SHIFT_TEST(ushll2, 2d, 4s, 15)
4363 GEN_SHIFT_TEST(ushll2, 2d, 4s, 31)
4367 GEN_SHIFT_TEST(ushll2, 4s, 8h, 0)
4368 GEN_SHIFT_TEST(ushll2, 4s, 8h, 7)
4369 GEN_SHIFT_TEST(ushll2, 4s, 8h, 15)
4373 GEN_SHIFT_TEST(ushll2, 8h, 16b, 0)
4374 GEN_SHIFT_TEST(ushll2, 8h, 16b, 3)
4375 GEN_SHIFT_TEST(ushll2, 8h, 16b, 7)
|
| D | fp_and_simd.stdout.exp | 28690 ushll2 v8.2d, v7.4s, #0 523d47a1f4bacd0d7ded886a0bf56713 00000000523d47a100000000f4bacd0d fpsr=00…
28691 ushll2 v8.2d, v7.4s, #15 af54904bcc6e0e98a8d13f63596a882c 000057aa4825800000006637074c0000 fpsr=0…
28692 ushll2 v8.2d, v7.4s, #31 9943f4ad945969c5fc7e275c65f588a0 4ca1fa56800000004a2cb4e280000000 fpsr=0…
28696 ushll2 v8.4s, v7.8h, #0 b32e059cfecb43f0decb1682ddb5ab22 0000b32e0000059c0000fecb000043f0 fpsr=00…
28697 ushll2 v8.4s, v7.8h, #7 d22045bda7463125f7b0c22749b698bb 006910000022de800053a30000189280 fpsr=00…
28698 ushll2 v8.4s, v7.8h, #15 45d3283e875e422402472676bb356bd6 22e98000141f000043af000021120000 fpsr=0…
28702 ushll2 v8.8h, v7.16b, #0 53db823821994226914a577f9bd62c88 005300db008200380021009900420026 fpsr=0…
28703 ushll2 v8.8h, v7.16b, #3 e318e9c04a4a0ef54aa027c1d6d31491 071800c00748060002500250007007a8 fpsr=0…
28704 ushll2 v8.8h, v7.16b, #7 8ffe7a50f20104b5bc9038545db7eb44 47807f003d0028007900008002005a80 fpsr=0…
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 2178 # CHECK: ushll2.8h v0, v0, #2
2180 # CHECK: ushll2.4s v0, v0, #4
2182 # CHECK: ushll2.2d v0, v0, #6
|
| D | neon-instructions.txt | 711 # CHECK: ushll2 v0.8h, v1.16b, #3
|
| /external/vixl/src/vixl/a64/ |
| D | simulator-a64.h | 2099 LogicVRegister ushll2(VectorFormat vform,
|
| D | assembler-a64.cc | 4260 void Assembler::ushll2(const VRegister& vd, in ushll2() function in vixl::Assembler
4276 ushll2(vd, vn, 0); in uxtl2()
|
| D | macro-assembler-a64.h | 2402 V(ushll2, Ushll2) \
|
| D | assembler-a64.h | 2883 void ushll2(const VRegister& vd,
|
| D | simulator-a64.cc | 3811 ushll2(vf, rd, rn, left_shift); in VisitNEONShiftImmediate()
|
| D | logic-a64.cc | 1664 LogicVRegister Simulator::ushll2(VectorFormat vform, in ushll2() function in vixl::Simulator
|
| /external/vixl/doc/ |
| D | supported-instructions.md | 4482 void ushll2(const VRegister& vd,
|