/external/llvm/test/CodeGen/AArch64/ |
D | fp16-vector-load-store.ll | 53 ; Load to one lane of v8f16 72 ; Simple store of v8f16 91 ; Store from one lane of v8f16 108 declare { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2.v8f16.p0v8f16(<8 x half>*) 109 declare { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3.v8f16.p0v8f16(<8 x half>*) 110 declare { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4.v8f16.p0v8f16(<8 … 111 declare void @llvm.aarch64.neon.st2.v8f16.p0v8f16(<8 x half>, <8 x half>, <8 x half>*) 112 declare void @llvm.aarch64.neon.st3.v8f16.p0v8f16(<8 x half>, <8 x half>, <8 x half>, <8 x half>*) 113 declare void @llvm.aarch64.neon.st4.v8f16.p0v8f16(<8 x half>, <8 x half>, <8 x half>, <8 x half>, <… 169 ; Load 2 x v8f16 with de-interleaving [all …]
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D | fp16-vector-nvcast.ll | 46 ; Test pattern (v8f16 (AArch64NvCast (v4i32 FPR128:$src))) 57 ; Test pattern (v8f16 (AArch64NvCast (v8i16 FPR128:$src))) 68 ; Test pattern (v8f16 (AArch64NvCast (v16i8 FPR128:$src))) 79 ; Test pattern (v8f16 (AArch64NvCast (v2i64 FPR128:$src)))
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D | arm64-aapcs.ll | 134 ; Check that v8f16 can be passed and returned in registers 148 ; Check that v8f16 can be passed and returned on the stack
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/external/llvm/include/llvm/CodeGen/ |
D | MachineValueType.h | 95 v8f16 = 44, // 8 x f16 enumerator 227 SimpleTy == MVT::v8f16 || SimpleTy == MVT::v4f32 || in is128BitVector() 315 case v8f16: return f16; in getVectorElementType() 348 case v8f16: in getVectorNumElements() 430 case v8f16: in getSizeInBits() 568 if (NumElements == 8) return MVT::v8f16; in getVectorVT()
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D | ValueTypes.td | 68 def v8f16 : ValueType<128, 44>; // 8 x f16 vector value
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/external/llvm/lib/Target/AArch64/ |
D | AArch64ISelDAGToDAG.cpp | 2264 else if (VT == MVT::v8i16 || VT == MVT::v8f16) in Select() 2282 else if (VT == MVT::v8i16 || VT == MVT::v8f16) in Select() 2300 else if (VT == MVT::v8i16 || VT == MVT::v8f16) in Select() 2318 else if (VT == MVT::v8i16 || VT == MVT::v8f16) in Select() 2336 else if (VT == MVT::v8i16 || VT == MVT::v8f16) in Select() 2354 else if (VT == MVT::v8i16 || VT == MVT::v8f16) in Select() 2372 else if (VT == MVT::v8i16 || VT == MVT::v8f16) in Select() 2390 else if (VT == MVT::v8i16 || VT == MVT::v8f16) in Select() 2408 else if (VT == MVT::v8i16 || VT == MVT::v8f16) in Select() 2423 VT == MVT::v8f16) in Select() [all …]
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D | AArch64CallingConvention.td | 33 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8], 68 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], 76 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], 88 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8], 104 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], 149 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], 158 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16], 177 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
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D | AArch64InstrInfo.td | 1230 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>; 1286 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>; 1439 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))), 1599 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))), 1912 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>; 2022 def : Pat<(store (v8f16 FPR128:$Rt), 2120 def : Pat<(store (v8f16 FPR128:$Rt), 2214 def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 2268 def : Pat<(post_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off), 2574 def : Pat<(v4f32 (fextend (v4f16 (extract_subvector (v8f16 V128:$Rn), [all …]
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D | AArch64ISelLowering.cpp | 118 addQRTypeForNEON(MVT::v8f16); in AArch64TargetLowering() 365 setOperationAction(ISD::FABS, MVT::v8f16, Expand); in AArch64TargetLowering() 366 setOperationAction(ISD::FADD, MVT::v8f16, Expand); in AArch64TargetLowering() 367 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand); in AArch64TargetLowering() 368 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand); in AArch64TargetLowering() 369 setOperationAction(ISD::FCOS, MVT::v8f16, Expand); in AArch64TargetLowering() 370 setOperationAction(ISD::FDIV, MVT::v8f16, Expand); in AArch64TargetLowering() 371 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand); in AArch64TargetLowering() 372 setOperationAction(ISD::FMA, MVT::v8f16, Expand); in AArch64TargetLowering() 373 setOperationAction(ISD::FMUL, MVT::v8f16, Expand); in AArch64TargetLowering() [all …]
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D | AArch64RegisterInfo.td | 400 v8f16],
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D | AArch64InstrFormats.td | 5275 def : Pat<(v8f16 (OpNode V128:$Rn, V128:$Rm)),
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/external/clang/test/CodeGen/ |
D | builtins-mips-msa.c | 13 typedef __fp16 v8f16 __attribute__ ((vector_size(16))); typedef 44 v8f16 v8f16_a = (v8f16) {0.5, 1, 2, 3, 4, 5, 6, 7}; in test() 45 v8f16 v8f16_b = (v8f16) {1.5, 2, 3, 4, 5, 6, 7, 8}; in test() 46 v8f16 v8f16_r; in test()
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/external/llvm/test/CodeGen/Mips/msa/ |
D | bitcast.ll | 56 ; are no operations for v8f16 to put in the way. 230 ; are no operations for v8f16 to put in the way. 354 ; are no operations for v8f16 to put in the way. 378 ; are no operations for v8f16 to put in the way. 401 ; are no operations for v8f16 to put in the way. 403 ; are no operations for v8f16 to put in the way. 423 ; are no operations for v8f16 to put in the way. 447 ; are no operations for v8f16 to put in the way. 471 ; are no operations for v8f16 to put in the way. 495 ; are no operations for v8f16 to put in the way. [all …]
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/external/llvm/lib/IR/ |
D | ValueTypes.cpp | 164 case MVT::v8f16: return "v8f16"; in getEVTString() 230 case MVT::v8f16: return VectorType::get(Type::getHalfTy(Context), 8); in getTypeForEVT()
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/external/llvm/lib/Target/Mips/ |
D | MipsMSAInstrInfo.td | 3551 def : MSAPat<(v8f16 (load addrimm10:$addr)), (LD_H addrimm10:$addr)>; 3555 def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10:$addr), 3583 def : MSABitconvertPat<v8i16, v8f16, MSA128H>; 3586 def : MSABitconvertPat<v8f16, v8i16, MSA128H>; 3594 def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>; 3607 def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>; 3613 def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>; 3619 def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>; 3625 def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>; 3682 def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>; [all …]
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D | MipsSEInstrInfo.cpp | 210 else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16)) in storeRegToStack() 251 else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16)) in loadRegFromStack()
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D | MipsRegisterInfo.td | 395 def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128,
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D | MipsSEISelLowering.cpp | 91 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass); in MipsSETargetLowering() 309 if (Ty != MVT::v8f16) { in addMSAFloatType()
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D | MipsISelLowering.cpp | 3381 else if (VT == MVT::v8i16 || VT == MVT::v8f16) in getRegForInlineAsmConstraint()
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/external/llvm/utils/TableGen/ |
D | CodeGenTarget.cpp | 104 case MVT::v8f16: return "MVT::v8f16"; in getEnumName()
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/external/llvm/include/llvm/IR/ |
D | Intrinsics.td | 186 def llvm_v8f16_ty : LLVMType<v8f16>; // 8 x half (__fp16)
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