| /external/llvm/test/CodeGen/ARM/ |
| D | saxpy10-a9.ll | 12 ; CHECK: vldr
13 ; CHECK: vldr
14 ; CHECK: vldr
15 ; CHECK: vldr
16 ; CHECK: vldr
17 ; CHECK-NEXT: vldr
21 ; CHECK-NEXT: vldr
22 ; CHECK-NEXT: vldr
26 ; CHECK-NEXT: vldr
29 ; CHECK-NEXT: vldr
[all …]
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| D | constantfp.ll | 18 ; CHECK-NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}}
27 ; CHECK-NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}}
46 ; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
55 ; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
63 ; CHECK: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
66 ; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
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| D | vbsl-constant.ll | 5 ;CHECK: vldr
6 ;CHECK: vldr
19 ;CHECK: vldr
20 ;CHECK: vldr
33 ;CHECK: vldr
34 ;CHECK: vldr
47 ;CHECK: vldr
48 ;CHECK: vldr
49 ;CHECK: vldr
|
| D | neon_ld1.ll | 4 ; CHECK: vldr d
5 ; CHECK: vldr d
19 ; CHECK: vldr d
20 ; CHECK: vldr d
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| D | 2010-05-21-BuildVector.ll | 13 ;CHECK: vldr s
20 ;CHECK: vldr s
27 ;CHECK: vldr s
34 ;CHECK: vldr s
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| D | 2014-02-05-vfp-regs-after-stack.ll | 9 ; CHECK: vldr s0, [sp, #8]
15 ; CHECK: vldr s0, [sp, #16]
21 ; CHECK: vldr s0, [sp, #8]
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| D | fpcmp-opt.ll | 11 ; CHECK: vldr [[S0:s[0-9]+]],
12 ; CHECK: vldr [[S1:s[0-9]+]],
35 ; CHECK-NOT: vldr
60 ; CHECK-NOT: vldr
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| D | fpmem.ll | 11 ; CHECK: vldr{{.*}}[
19 ; CHECK: vldr{{.*}}, #4]
28 ; CHECK: vldr{{.*}}, #-4]
|
| D | fastcc-vfp.ll | 7 ; CHECK: vldr
17 ; CHECK: vldr
25 ; CHECK: vldr
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| D | subreg-remat.ll | 15 ; CHECK: vldr s1, LCPI
20 ; CHECK: vldr [[D16:d[0-9]+]],
40 ; CHECK: vldr s0, LCPI
45 ; CHECK: vldr [[S0:s[0-9]+]], LCPI
|
| D | neon_fpconv.ll | 23 ; CHECK: vldr
35 ; CHECK: vldr
|
| D | vldm-liveness.ll | 22 ; CHECK: vldr s3, [r0, #8]
24 ; CHECK: vldr s2, [r0, #16]
|
| D | fast-isel-cmp-imm.ll | 30 ; ARM: vldr
32 ; THUMB: vldr
67 ; ARM: vldr
69 ; THUMB: vldr
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| D | memcpy-inline.ll | 19 ; CHECK: vldr [[REG1:d[0-9]+]],
62 ; CHECK: vldr d{{[0-9]+}}, [r1]
100 ; CHECK: vldr [[REG9:d[0-9]+]], [r0]
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| D | 2009-09-24-spill-align.ll | 9 ; CHECK: vldr
|
| /external/llvm/test/MC/ARM/ |
| D | simple-fp-encoding.s | 228 @ CHECK: vldr d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed]
229 @ CHECK: vldr s0, [lr] @ encoding: [0x00,0x0a,0x9e,0xed]
230 @ CHECK: vldr d0, [lr] @ encoding: [0x00,0x0b,0x9e,0xed]
232 vldr.64 d17, [r0]
233 vldr.i32 s0, [lr]
234 vldr.d d0, [lr]
236 @ CHECK: vldr d1, [r2, #32] @ encoding: [0x08,0x1b,0x92,0xed]
237 @ CHECK: vldr d1, [r2, #-32] @ encoding: [0x08,0x1b,0x12,0xed]
238 vldr.64 d1, [r2, #32]
239 vldr.f64 d1, [r2, #-32]
[all …]
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| D | directive-fpu-instrs.s | 5 vldr d21, [r7, #296] label
13 vldr d21, [r7, #296] label
|
| /external/llvm/test/Transforms/LoopVectorize/ARM/ |
| D | mul-cast-vect.ll | 34 ; ASM: vldr
36 ; ASM: vldr
51 ; ASM: vldr
53 ; ASM: vldr
68 ; ASM: vldr
70 ; ASM: vldr
85 ; ASM: vldr
87 ; ASM: vldr
|
| /external/boringssl/src/crypto/chacha/ |
| D | chacha_vec_arm.S | 102 vldr d24, [r3, #64]
103 vldr d25, [r3, #72]
110 vldr d26, [r2, #80]
111 vldr d27, [r2, #88]
121 vldr d28, [r1, #80]
122 vldr d29, [r1, #88]
129 vldr d22, [r7, #128]
130 vldr d23, [r7, #136]
136 vldr d0, .L91 define
137 vldr d1, .L91+8 define
[all …]
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | fp-encoding.txt | 163 # CHECK: vldr d17, [r0]
167 # CHECK: vldr d1, [r2, #32]
168 # CHECK: vldr d1, [r2, #-32]
171 # CHECK: vldr d2, [r3]
174 # CHECK: vldr d3, [pc]
177 # CHECK: vldr s13, [r0]
181 # CHECK: vldr s1, [r2, #32]
182 # CHECK: vldr s1, [r2, #-32]
185 # CHECK: vldr s2, [r3]
188 # CHECK: vldr s5, [pc]
|
| D | invalid-IT-CC15.txt | 15 # vldr d19, [pc, #388]
18 # vldr<und> d16, [pc, #384]
|
| /external/v8/src/arm/ |
| D | lithium-gap-resolver-arm.cc | 171 __ vldr(kScratchDoubleReg, cgen_->ToMemOperand(source)); in BreakCycle() local
227 __ vldr(kScratchDoubleReg.low(), source_operand); in EmitMove() local
277 __ vldr(cgen_->ToDoubleRegister(destination), source_operand); in EmitMove() local
284 __ vldr(kScratchDoubleReg, source_operand); in EmitMove() local
288 __ vldr(kScratchDoubleReg, source_operand); in EmitMove() local
|
| /external/llvm/test/CodeGen/Thumb2/ |
| D | aapcs.ll | 29 ; HARD: vldr s0, [sp]
38 ; HARD: vldr d0, [sp]
47 ; HARD: vldr d0, [sp]
|
| D | inflate-regs.ll | 9 ; CHECK: vldr s
28 ; CHECK: vldr s
|
| /external/v8/test/cctest/ |
| D | test-disasm-arm.cc | 510 COMPARE(vldr(s0, r0, 0), in TEST()
512 COMPARE(vldr(s1, r1, 4), in TEST()
514 COMPARE(vldr(s15, r4, 16), in TEST()
516 COMPARE(vldr(s16, r5, 20), in TEST()
518 COMPARE(vldr(s31, r10, 1020), in TEST()
532 COMPARE(vldr(d0, r0, 0), in TEST()
534 COMPARE(vldr(d1, r1, 4), in TEST()
536 COMPARE(vldr(d15, r10, 1020), in TEST()
644 COMPARE(vldr(d25, r0, 0), in TEST()
646 COMPARE(vldr(d26, r1, 4), in TEST()
[all …]
|