| /external/mesa3d/src/gallium/drivers/nv30/ |
| D | nv30_screen.c | 462 PUSH_DATA (push, fifo->vram); /* TEXTURE0 */ in nv30_screen_create()
464 PUSH_DATA (push, fifo->vram); /* COLOR1 */ in nv30_screen_create()
466 PUSH_DATA (push, fifo->vram); /* COLOR0 */ in nv30_screen_create()
467 PUSH_DATA (push, fifo->vram); /* ZETA */ in nv30_screen_create()
468 PUSH_DATA (push, fifo->vram); /* VTXBUF0 */ in nv30_screen_create()
494 PUSH_DATA (push, fifo->vram); in nv30_screen_create()
495 PUSH_DATA (push, fifo->vram); /* COLOR3 */ in nv30_screen_create()
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| D | nv30_transfer.c | 439 PUSH_RELOC(push, dst->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv30_transfer_rect_sifm()
440 PUSH_RELOC(push, dst->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv30_transfer_rect_sifm()
450 PUSH_RELOC(push, dst->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv30_transfer_rect_sifm()
460 PUSH_RELOC(push, src->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv30_transfer_rect_sifm()
512 PUSH_DATA (push, (src->domain == NOUVEAU_BO_VRAM) ? fifo->vram : fifo->gart); in nv30_transfer_rect_m2mf()
513 PUSH_DATA (push, (dst->domain == NOUVEAU_BO_VRAM) ? fifo->vram : fifo->gart); in nv30_transfer_rect_m2mf()
704 PUSH_DATA (push, (s_dom == NOUVEAU_BO_VRAM) ? fifo->vram : fifo->gart); in nv30_transfer_copy_data()
705 PUSH_DATA (push, (d_dom == NOUVEAU_BO_VRAM) ? fifo->vram : fifo->gart); in nv30_transfer_copy_data()
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| /external/mesa3d/src/mesa/drivers/dri/nouveau/ |
| D | nv04_context.c | 88 PUSH_DATA (push, fifo->vram); in nv04_hwctx_init()
89 PUSH_DATA (push, fifo->vram); in nv04_hwctx_init()
95 PUSH_DATA (push, fifo->vram); in nv04_hwctx_init()
103 PUSH_DATA (push, fifo->vram); in nv04_hwctx_init()
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| D | nv20_context.c | 109 PUSH_DATA (push, fifo->vram); in nv20_hwctx_init()
112 PUSH_DATA (push, fifo->vram); in nv20_hwctx_init()
113 PUSH_DATA (push, fifo->vram); in nv20_hwctx_init()
115 PUSH_DATA (push, fifo->vram); in nv20_hwctx_init()
173 PUSH_DATA (push, fifo->vram); in nv20_hwctx_init()
175 PUSH_DATA (push, fifo->vram); in nv20_hwctx_init()
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| D | nv04_surface.c | 234 PUSH_DATA (push, fifo->vram); in nv04_surface_copy_swizzle()
242 PUSH_RELOC(push, src->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv04_surface_copy_swizzle()
298 PUSH_RELOC(push, src->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv04_surface_copy_m2mf()
299 PUSH_RELOC(push, dst->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv04_surface_copy_m2mf()
441 PUSH_RELOC(push, dst->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv04_surface_fill()
442 PUSH_RELOC(push, dst->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart); in nv04_surface_fill()
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| D | nv10_context.c | 214 PUSH_DATA (push, fifo->vram); in nv10_hwctx_init()
218 PUSH_DATA (push, fifo->vram); in nv10_hwctx_init()
219 PUSH_DATA (push, fifo->vram); in nv10_hwctx_init()
250 PUSH_DATA (push, fifo->vram); in nv10_hwctx_init()
251 PUSH_DATA (push, fifo->vram); in nv10_hwctx_init()
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| D | nouveau_context.c | 152 .vram = 0xbeef0201, in nouveau_context_init()
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| /external/mesa3d/src/gallium/drivers/nv50/ |
| D | nv50_screen.c | 339 PUSH_DATA (push, fifo->vram); in nv50_screen_init_hwctx()
340 PUSH_DATA (push, fifo->vram); in nv50_screen_init_hwctx()
346 PUSH_DATA (push, fifo->vram); in nv50_screen_init_hwctx()
347 PUSH_DATA (push, fifo->vram); in nv50_screen_init_hwctx()
348 PUSH_DATA (push, fifo->vram); in nv50_screen_init_hwctx()
368 PUSH_DATA(push, fifo->vram); in nv50_screen_init_hwctx()
371 PUSH_DATA(push, fifo->vram); in nv50_screen_init_hwctx()
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| /external/libdrm/nouveau/ |
| D | nouveau.c | 78 uint64_t chipset, vram, gart, bousage; in nouveau_device_wrap() local
112 ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_FB_SIZE, &vram); in nouveau_device_wrap()
140 nvdev->base.vram_size = vram; in nouveau_device_wrap()
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| D | nouveau.h | 34 uint32_t vram; member
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| D | abi16.c | 41 struct drm_nouveau_channel_alloc req = {nv04->vram, nv04->gart}; in abi16_chan_nv04()
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| /external/mesa3d/src/gallium/winsys/radeon/drm/ |
| D | radeon_winsys.h | 319 boolean (*cs_memory_below_limit)(struct radeon_winsys_cs *cs, uint64_t vram, uint64_t gtt);
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| D | radeon_drm_cs.c | 369 static boolean radeon_drm_cs_memory_below_limit(struct radeon_winsys_cs *rcs, uint64_t vram, uint64… in radeon_drm_cs_memory_below_limit() argument
374 (cs->csc->used_vram + vram) < cs->ws->info.vram_size * 0.7; in radeon_drm_cs_memory_below_limit()
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| /external/mesa3d/src/gallium/drivers/nouveau/ |
| D | nouveau_screen.c | 123 struct nv04_fifo nv04_data = { .vram = 0xbeef0201, .gart = 0xbeef0202 }; in nouveau_screen_init()
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| D | nouveau_video.c | 515 struct nv04_fifo nv04_data = { .vram = 0xbeef0201, .gart = 0xbeef0202 }; in nouveau_create_decoder()
615 PUSH_DATA (push, nv04_data.vram); in nouveau_create_decoder()
632 PUSH_DATA (push, nv04_data.vram); in nouveau_create_decoder()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_hw_context.c | 638 if (!ctx->ws->cs_memory_below_limit(ctx->cs, ctx->vram, ctx->gtt)) { in r600_need_cs_space()
640 ctx->vram = 0; in r600_need_cs_space()
646 ctx->vram = 0; in r600_need_cs_space()
967 ctx->vram = 0; in r600_context_flush()
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| D | r600_pipe.h | 375 uint64_t vram; member
913 rctx->vram += rr->buf->size; in r600_context_add_resource_size()
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