Lines Matching refs:dd

626   virtual void vmovd(DRegister dd, DRegister dm, Condition cond = AL) = 0;
630   virtual bool vmovd(DRegister dd, double d_imm, Condition cond = AL) = 0;
634   virtual void vldrd(DRegister dd, const Address& ad, Condition cond = AL) = 0;
635   virtual void vstrd(DRegister dd, const Address& ad, Condition cond = AL) = 0;
638   virtual void vaddd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) = 0;
640   virtual void vsubd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) = 0;
642   virtual void vmuld(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) = 0;
644   virtual void vmlad(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) = 0;
646   virtual void vmlsd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) = 0;
648   virtual void vdivd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) = 0;
651   virtual void vabsd(DRegister dd, DRegister dm, Condition cond = AL) = 0;
653   virtual void vnegd(DRegister dd, DRegister dm, Condition cond = AL) = 0;
655   virtual void vsqrtd(DRegister dd, DRegister dm, Condition cond = AL) = 0;
658   virtual void vcvtds(DRegister dd, SRegister sm, Condition cond = AL) = 0;
662   virtual void vcvtdi(DRegister dd, SRegister sm, Condition cond = AL) = 0;
666   virtual void vcvtdu(DRegister dd, SRegister sm, Condition cond = AL) = 0;
669   virtual void vcmpd(DRegister dd, DRegister dm, Condition cond = AL) = 0;
671   virtual void vcmpdz(DRegister dd, Condition cond = AL) = 0;
722   virtual void LoadLiteral(DRegister dd, Literal* literal) = 0;