115   bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
119                           unsigned RegA, unsigned RegB, unsigned Dist);
534 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {  in regsAreCompatible()  argument
535   if (RegA == RegB)  in regsAreCompatible()
537   if (!RegA || !RegB)  in regsAreCompatible()
539   return TRI->regsOverlap(RegA, RegB);  in regsAreCompatible()
665     unsigned RegA = MI->getOperand(0).getReg();  in commuteInstruction()  local
666     SrcRegMap[RegA] = FromRegC;  in commuteInstruction()
675 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){  in isProfitableToConv3Addr()  argument
685   unsigned ToRegA = getMappedReg(RegA, DstRegMap);  in isProfitableToConv3Addr()
694                                               unsigned RegA, unsigned RegB,  in convertInstTo3Addr()  argument
726   SrcRegMap.erase(RegA);  in convertInstTo3Addr()
1468     unsigned RegA = DstMO.getReg();  in processTiedPairs()  local
1475     if (RegA == RegB) {  in processTiedPairs()
1482     LastCopiedReg = RegA;  in processTiedPairs()
1494              MI->getOperand(i).getReg() != RegA);  in processTiedPairs()
1499                                       TII->get(TargetOpcode::COPY), RegA);  in processTiedPairs()
1505       if (TargetRegisterInfo::isVirtualRegister(RegA)) {  in processTiedPairs()
1506         assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),  in processTiedPairs()
1513         assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))  in processTiedPairs()
1527       if (TargetRegisterInfo::isVirtualRegister(RegA)) {  in processTiedPairs()
1528         LiveInterval &LI = LIS->getInterval(RegA);  in processTiedPairs()
1547     if (TargetRegisterInfo::isVirtualRegister(RegA) &&  in processTiedPairs()
1549       MRI->constrainRegClass(RegA, RC);  in processTiedPairs()
1550     MO.setReg(RegA);  in processTiedPairs()
1557     SrcRegMap[RegA] = RegB;  in processTiedPairs()