Lines Matching refs:V128
3907 def XDHighr : BaseUnscaledConversionToHigh<0b01, 0b111, GPR64, V128,
3913 def DXHighr : BaseUnscaledConversionFromHigh<0b01, 0b110, V128, GPR64,
4369 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b001, opc, V128,
4371 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4375 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b011, opc, V128,
4377 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4381 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b101, opc, V128,
4383 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4384 def v2i64 : BaseSIMDThreeSameVector<1, U, 0b111, opc, V128,
4386 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
4395 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b001, opc, V128,
4397 [(set V128:$Rd, (v16i8 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm))))]>;
4401 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b011, opc, V128,
4403 [(set V128:$Rd, (v8i16 (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm))))]>;
4407 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b101, opc, V128,
4409 [(set V128:$Rd, (v4i32 (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm))))]>;
4418 def v16i8 : BaseSIMDThreeSameVectorTied<1, U, 0b001, opc, V128,
4420 [(set (v16i8 V128:$dst),
4421 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4426 def v8i16 : BaseSIMDThreeSameVectorTied<1, U, 0b011, opc, V128,
4428 [(set (v8i16 V128:$dst),
4429 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4434 def v4i32 : BaseSIMDThreeSameVectorTied<1, U, 0b101, opc, V128,
4436 [(set (v4i32 V128:$dst),
4437 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4446 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b001, opc, V128,
4448 [(set (v16i8 V128:$Rd),
4449 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4459 def v8f16 : BaseSIMDThreeSameVector<1, U, {S,0b10}, {0b00,opc}, V128,
4461 [(set (v8f16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>;
4466 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0b01}, {0b11,opc}, V128,
4468 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4469 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,0b11}, {0b11,opc}, V128,
4471 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4481 def v8f16 : BaseSIMDThreeSameVector<1, U, {S,0b10}, {0b00,opc}, V128,
4483 [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>;
4488 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0b01}, {0b11,opc}, V128,
4490 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4491 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,0b11}, {0b11,opc}, V128,
4493 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4503 def v8f16 : BaseSIMDThreeSameVectorTied<1, U, {S,0b10}, {0b00,opc}, V128,
4505 [(set (v8f16 V128:$dst),
4506 (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>;
4512 def v4f32 : BaseSIMDThreeSameVectorTied<1, U, {S,0b01}, {0b11,opc}, V128,
4514 [(set (v4f32 V128:$dst),
4515 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4516 def v2f64 : BaseSIMDThreeSameVectorTied<1, U, {S,0b11}, {0b11,opc}, V128,
4518 [(set (v2f64 V128:$dst),
4519 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4528 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b011, opc, V128,
4530 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4534 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b101, opc, V128,
4536 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4545 def v16i8 : BaseSIMDThreeSameVector<1, U, {size,1}, 0b00011, V128,
4547 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn, V128:$Rm))]>;
4556 def : Pat<(v8i16 (OpNode V128:$LHS, V128:$RHS)),
4557 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4558 def : Pat<(v4i32 (OpNode V128:$LHS, V128:$RHS)),
4559 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4560 def : Pat<(v2i64 (OpNode V128:$LHS, V128:$RHS)),
4561 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4570 def v16i8 : BaseSIMDThreeSameVectorTied<1, U, {size,1}, 0b00011, V128,
4572 [(set (v16i8 V128:$dst),
4573 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
4574 (v16i8 V128:$Rm)))]>;
4589 def : Pat<(v8i16 (OpNode (v8i16 V128:$LHS), (v8i16 V128:$MHS),
4590 (v8i16 V128:$RHS))),
4592 V128:$LHS, V128:$MHS, V128:$RHS)>;
4593 def : Pat<(v4i32 (OpNode (v4i32 V128:$LHS), (v4i32 V128:$MHS),
4594 (v4i32 V128:$RHS))),
4596 V128:$LHS, V128:$MHS, V128:$RHS)>;
4597 def : Pat<(v2i64 (OpNode (v2i64 V128:$LHS), (v2i64 V128:$MHS),
4598 (v2i64 V128:$RHS))),
4600 V128:$LHS, V128:$MHS, V128:$RHS)>;
4663 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, 0b00, V128,
4665 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4669 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
4671 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4675 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, 0b00, V128,
4677 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4683 : I<(outs V128:$Rd), (ins regtype:$Rn), asm,
4702 def v16i8 : BaseSIMDVectorLShiftLongBySize<1, 0b00, V128,
4706 def v8i16 : BaseSIMDVectorLShiftLongBySize<1, 0b01, V128,
4710 def v4i32 : BaseSIMDVectorLShiftLongBySize<1, 0b10, V128,
4721 def v16i8_v8i16 : BaseSIMDTwoSameVector<1, U, 0b00, opc, 0b00, V128,
4723 [(set (v8i16 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4727 def v8i16_v4i32 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
4729 [(set (v4i32 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4733 def v4i32_v2i64 : BaseSIMDTwoSameVector<1, U, 0b10, opc, 0b00, V128,
4735 [(set (v2i64 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4744 def v16i8_v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, 0b00, V128,
4746 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd),
4747 (v16i8 V128:$Rn)))]>;
4752 def v8i16_v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, 0b00, V128,
4754 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd),
4755 (v8i16 V128:$Rn)))]>;
4760 def v4i32_v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, 0b00, V128,
4762 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd),
4763 (v4i32 V128:$Rn)))]>;
4772 def v16i8 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, 0b00, V128,
4774 [(set (v16i8 V128:$dst), (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
4778 def v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, 0b00, V128,
4780 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn)))]>;
4784 def v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, 0b00, V128,
4786 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
4787 def v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b11, opc, 0b00, V128,
4789 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn)))]>;
4797 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, 0b00, V128,
4799 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4803 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
4805 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4809 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, 0b00, V128,
4811 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4812 def v2i64 : BaseSIMDTwoSameVector<1, U, 0b11, opc, 0b00, V128,
4814 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4824 def v16i8 : BaseSIMDTwoSameVector<1, U, size, opc, 0b00, V128,
4826 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4836 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, 0b00, V128,
4838 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn))]>;
4842 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
4844 [(set (v8i16 V128:$Rd), (OpNode V128:$Rn))]>;
4855 def v8f16 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b11, V128,
4857 [(set (v8f16 V128:$Rd), (OpNode (v8f16 V128:$Rn)))]>;
4862 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128,
4864 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4865 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b00, V128,
4867 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4876 def v4i32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128,
4878 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4888 def v8f16 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b11, V128,
4890 [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn)))]>;
4895 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128,
4897 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4898 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b00, V128,
4900 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4909 def v8f16 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b11, V128,
4911 [(set (v8f16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4916 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, 0b00, V128,
4918 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4919 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, 0b00, V128,
4921 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4971 def v8i8 : BaseSIMDMixedTwoVector<0, U, 0b00, opc, V128, V64,
4973 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4974 def v16i8 : BaseSIMDMixedTwoVectorTied<1, U, 0b00, opc, V128, V128,
4976 def v4i16 : BaseSIMDMixedTwoVector<0, U, 0b01, opc, V128, V64,
4978 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4979 def v8i16 : BaseSIMDMixedTwoVectorTied<1, U, 0b01, opc, V128, V128,
4981 def v2i32 : BaseSIMDMixedTwoVector<0, U, 0b10, opc, V128, V64,
4983 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4984 def v4i32 : BaseSIMDMixedTwoVectorTied<1, U, 0b10, opc, V128, V128,
4987 def : Pat<(concat_vectors (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn))),
4989 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4990 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn))),
4992 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4993 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn))),
4995 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
5029 def v16i8rz : BaseSIMDCmpTwoVector<1, U, 0b00, 0b00, opc, V128,
5035 def v8i16rz : BaseSIMDCmpTwoVector<1, U, 0b01, 0b00, opc, V128,
5041 def v4i32rz : BaseSIMDCmpTwoVector<1, U, 0b10, 0b00, opc, V128,
5044 def v2i64rz : BaseSIMDCmpTwoVector<1, U, 0b11, 0b00, opc, V128,
5057 def v8i16rz : BaseSIMDCmpTwoVector<1, U, {S,1}, 0b11, opc, V128,
5064 def v4i32rz : BaseSIMDCmpTwoVector<1, U, {S,0}, 0b00, opc, V128,
5067 def v2i64rz : BaseSIMDCmpTwoVector<1, U, {S,1}, 0b00, opc, V128,
5075 (!cast<Instruction>(NAME # v8i16rz) V128:$Vd, V128:$Vn), 0>;
5080 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
5082 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
5087 (!cast<Instruction>(NAME # v8i16rz) V128:$Vd, V128:$Vn), 0>;
5092 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
5094 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
5141 def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V128, V64,
5143 def v8i16 : BaseSIMDFPCvtTwoVector<1, U, {S,0}, opc, V128, V128,
5145 def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V128, V64,
5147 def v4i32 : BaseSIMDFPCvtTwoVector<1, U, {S,1}, opc, V128, V128,
5152 def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V64, V128,
5154 def v8i16 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,0}, opc, V128, V128,
5156 def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128,
5158 def v4i32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128,
5164 def v2f32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128,
5166 [(set (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
5167 def v4f32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128,
5170 def : Pat<(concat_vectors (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn))),
5172 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
5238 V64, V128, V128,
5240 [(set (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
5242 V128, V128, V128,
5246 V64, V128, V128,
5248 [(set (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
5250 V128, V128, V128,
5254 V64, V128, V128,
5256 [(set (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
5258 V128, V128, V128,
5265 def : Pat<(concat_vectors (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn),
5266 (v8i16 V128:$Rm))),
5269 V128:$Rn, V128:$Rm)>;
5270 def : Pat<(concat_vectors (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn),
5271 (v4i32 V128:$Rm))),
5274 V128:$Rn, V128:$Rm)>;
5275 def : Pat<(concat_vectors (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn),
5276 (v2i64 V128:$Rm))),
5279 V128:$Rn, V128:$Rm)>;
5285 V128, V64, V64,
5287 [(set (v8i16 V128:$Rd), (IntOp (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5289 V128, V128, V128,
5293 V128, V64, V64,
5296 V128, V128, V128,
5300 def : Pat<(v8i16 (IntOp (v8i8 (extract_high_v16i8 V128:$Rn)),
5301 (v8i8 (extract_high_v16i8 V128:$Rm)))),
5302 (!cast<Instruction>(NAME#"v16i8") V128:$Rn, V128:$Rm)>;
5308 V128, V64, V64,
5310 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5312 V128, V128, V128,
5314 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
5315 (extract_high_v8i16 V128:$Rm)))]>;
5317 V128, V64, V64,
5319 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5321 V128, V128, V128,
5323 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
5324 (extract_high_v4i32 V128:$Rm)))]>;
5330 V128, V64, V64,
5332 [(set (v8i16 V128:$Rd),
5335 V128, V128, V128,
5337 [(set (v8i16 V128:$Rd),
5338 (zext (v8i8 (OpNode (extract_high_v16i8 V128:$Rn),
5339 (extract_high_v16i8 V128:$Rm)))))]>;
5341 V128, V64, V64,
5343 [(set (v4i32 V128:$Rd),
5346 V128, V128, V128,
5348 [(set (v4i32 V128:$Rd),
5349 (zext (v4i16 (OpNode (extract_high_v8i16 V128:$Rn),
5350 (extract_high_v8i16 V128:$Rm)))))]>;
5352 V128, V64, V64,
5354 [(set (v2i64 V128:$Rd),
5357 V128, V128, V128,
5359 [(set (v2i64 V128:$Rd),
5360 (zext (v2i32 (OpNode (extract_high_v4i32 V128:$Rn),
5361 (extract_high_v4i32 V128:$Rm)))))]>;
5368 V128, V64, V64,
5370 [(set (v8i16 V128:$dst),
5371 (add (v8i16 V128:$Rd),
5374 V128, V128, V128,
5376 [(set (v8i16 V128:$dst),
5377 (add (v8i16 V128:$Rd),
5378 (zext (v8i8 (OpNode (extract_high_v16i8 V128:$Rn),
5379 (extract_high_v16i8 V128:$Rm))))))]>;
5381 V128, V64, V64,
5383 [(set (v4i32 V128:$dst),
5384 (add (v4i32 V128:$Rd),
5387 V128, V128, V128,
5389 [(set (v4i32 V128:$dst),
5390 (add (v4i32 V128:$Rd),
5391 (zext (v4i16 (OpNode (extract_high_v8i16 V128:$Rn),
5392 (extract_high_v8i16 V128:$Rm))))))]>;
5394 V128, V64, V64,
5396 [(set (v2i64 V128:$dst),
5397 (add (v2i64 V128:$Rd),
5400 V128, V128, V128,
5402 [(set (v2i64 V128:$dst),
5403 (add (v2i64 V128:$Rd),
5404 (zext (v2i32 (OpNode (extract_high_v4i32 V128:$Rn),
5405 (extract_high_v4i32 V128:$Rm))))))]>;
5411 V128, V64, V64,
5413 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5415 V128, V128, V128,
5417 [(set (v8i16 V128:$Rd), (OpNode (extract_high_v16i8 V128:$Rn),
5418 (extract_high_v16i8 V128:$Rm)))]>;
5420 V128, V64, V64,
5422 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5424 V128, V128, V128,
5426 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
5427 (extract_high_v8i16 V128:$Rm)))]>;
5429 V128, V64, V64,
5431 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5433 V128, V128, V128,
5435 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
5436 (extract_high_v4i32 V128:$Rm)))]>;
5443 V128, V64, V64,
5445 [(set (v8i16 V128:$dst),
5446 (OpNode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5448 V128, V128, V128,
5450 [(set (v8i16 V128:$dst),
5451 (OpNode (v8i16 V128:$Rd),
5452 (extract_high_v16i8 V128:$Rn),
5453 (extract_high_v16i8 V128:$Rm)))]>;
5455 V128, V64, V64,
5457 [(set (v4i32 V128:$dst),
5458 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5460 V128, V128, V128,
5462 [(set (v4i32 V128:$dst),
5463 (OpNode (v4i32 V128:$Rd),
5464 (extract_high_v8i16 V128:$Rn),
5465 (extract_high_v8i16 V128:$Rm)))]>;
5467 V128, V64, V64,
5469 [(set (v2i64 V128:$dst),
5470 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5472 V128, V128, V128,
5474 [(set (v2i64 V128:$dst),
5475 (OpNode (v2i64 V128:$Rd),
5476 (extract_high_v4i32 V128:$Rn),
5477 (extract_high_v4i32 V128:$Rm)))]>;
5483 V128, V64, V64,
5485 [(set (v4i32 V128:$dst),
5486 (Accum (v4i32 V128:$Rd),
5490 V128, V128, V128,
5492 [(set (v4i32 V128:$dst),
5493 (Accum (v4i32 V128:$Rd),
5494 (v4i32 (int_aarch64_neon_sqdmull (extract_high_v8i16 V128:$Rn),
5495 (extract_high_v8i16 V128:$Rm)))))]>;
5497 V128, V64, V64,
5499 [(set (v2i64 V128:$dst),
5500 (Accum (v2i64 V128:$Rd),
5504 V128, V128, V128,
5506 [(set (v2i64 V128:$dst),
5507 (Accum (v2i64 V128:$Rd),
5508 (v2i64 (int_aarch64_neon_sqdmull (extract_high_v4i32 V128:$Rn),
5509 (extract_high_v4i32 V128:$Rm)))))]>;
5515 V128, V128, V64,
5517 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i8 V64:$Rm)))]>;
5519 V128, V128, V128,
5521 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
5522 (extract_high_v16i8 V128:$Rm)))]>;
5524 V128, V128, V64,
5526 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i16 V64:$Rm)))]>;
5528 V128, V128, V128,
5530 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
5531 (extract_high_v8i16 V128:$Rm)))]>;
5533 V128, V128, V64,
5535 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i32 V64:$Rm)))]>;
5537 V128, V128, V128,
5539 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
5540 (extract_high_v4i32 V128:$Rm)))]>;
5575 def v16i8 : BaseSIMDBitwiseExtract<1, V128, v16i8, asm, ".16b">;
5609 def v16i8 : BaseSIMDZipVector<0b001, opc, V128,
5613 def v8i16 : BaseSIMDZipVector<0b011, opc, V128,
5617 def v4i32 : BaseSIMDZipVector<0b101, opc, V128,
5619 def v2i64 : BaseSIMDZipVector<0b111, opc, V128,
5624 def : Pat<(v8f16 (OpNode V128:$Rn, V128:$Rm)),
5625 (!cast<Instruction>(NAME#"v8i16") V128:$Rn, V128:$Rm)>;
5628 def : Pat<(v4f32 (OpNode V128:$Rn, V128:$Rm)),
5629 (!cast<Instruction>(NAME#"v4i32") V128:$Rn, V128:$Rm)>;
5630 def : Pat<(v2f64 (OpNode V128:$Rn, V128:$Rm)),
5631 (!cast<Instruction>(NAME#"v2i64") V128:$Rn, V128:$Rm)>;
6003 def v2i64p : BaseSIMDPairwiseScalar<U, 0b11, opc, FPR64Op, V128,
6014 def v2i64p : BaseSIMDPairwiseScalar<1, {S,1}, opc, FPR64Op, V128,
6047 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR8, V128,
6051 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR16, V128,
6053 def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR32, V128,
6060 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR16, V128,
6064 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR32, V128,
6066 def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR64, V128,
6076 def v8i16v : BaseSIMDAcrossLanes<1, 0, {sz1, 0}, opcode, FPR16, V128,
6078 [(set FPR16:$Rd, (intOp (v8f16 V128:$Rn)))]>;
6080 def v4i32v : BaseSIMDAcrossLanes<1, 1, {sz1, 0}, opcode, FPR32, V128,
6082 [(set FPR32:$Rd, (intOp (v4f32 V128:$Rn)))]>;
6121 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins V128:$Rn, idxtype:$idx), "dup",
6125 (OpNode (insreg V128:$Rn), idxtype:$idx))]> {
6130 : SIMDDupFromElement<1, ".2d", ".d", v2i64, v2i64, V128,
6166 : BaseSIMDInsDup<Q, 0, (outs regtype:$Rd), (ins V128:$Rn, idxtype:$idx), asm,
6178 [(set regtype:$Rd, (vector_extract (vectype V128:$Rn), idxtype:$idx))]>;
6184 (inst regtype:$dst, V128:$src, idxtype:$idx)>;
6245 : BaseSIMDInsDup<1, 0, (outs V128:$dst),
6246 (ins V128:$Rd, idxtype:$idx, regtype:$Rn), "ins",
6250 [(set V128:$dst,
6251 (vector_insert (vectype V128:$Rd), regtype:$Rn, idxtype:$idx))]> {
6257 : BaseSIMDInsDup<1, 1, (outs V128:$dst),
6258 (ins V128:$Rd, idxtype:$idx, V128:$Rn, idxtype:$idx2), "ins",
6262 [(set V128:$dst,
6264 (vectype V128:$Rd),
6265 (elttype (vector_extract (vectype V128:$Rn), idxtype:$idx2)),
6272 (inst V128:$dst, idxtype:$idx, regtype:$src)>;
6277 (inst V128:$dst, idxtype:$idx, V128:$src, idxtype:$idx2)>;
6416 def v16i8One : BaseSIMDTableLookup<1, 0b00, op, V128, VecListOne16b,
6418 def v16i8Two : BaseSIMDTableLookup<1, 0b01, op, V128, VecListTwo16b,
6420 def v16i8Three: BaseSIMDTableLookup<1, 0b10, op, V128, VecListThree16b,
6422 def v16i8Four : BaseSIMDTableLookup<1, 0b11, op, V128, VecListFour16b,
6439 V128, VecListOne128>;
6442 V128, VecListTwo128>;
6445 V128, VecListThree128>;
6448 V128, VecListFour128>;
6460 def v16i8One : BaseSIMDTableLookupTied<1, 0b00, op, V128, VecListOne16b,
6462 def v16i8Two : BaseSIMDTableLookupTied<1, 0b01, op, V128, VecListTwo16b,
6464 def v16i8Three: BaseSIMDTableLookupTied<1, 0b10, op, V128, VecListThree16b,
6466 def v16i8Four : BaseSIMDTableLookupTied<1, 0b11, op, V128, VecListFour16b,
6483 V128, VecListOne128>;
6486 V128, VecListTwo128>;
6489 V128, VecListThree128>;
6492 V128, VecListFour128>;
6522 def i8 : BaseSIMDScalarCPY<FPR8, V128, ".b", VectorIndexB> {
6527 def i16 : BaseSIMDScalarCPY<FPR16, V128, ".h", VectorIndexH> {
6532 def i32 : BaseSIMDScalarCPY<FPR32, V128, ".s", VectorIndexS> {
6537 def i64 : BaseSIMDScalarCPY<FPR64, V128, ".d", VectorIndexD> {
6543 def : Pat<(v1i64 (scalar_to_vector (i64 (vector_extract (v2i64 V128:$src),
6545 (!cast<Instruction>(NAME # i64) V128:$src, VectorIndexD:$idx)>;
6550 FPR8, V128, VectorIndexB>;
6553 FPR16, V128, VectorIndexH>;
6556 FPR32, V128, VectorIndexS>;
6559 FPR64, V128, VectorIndexD>;
6663 def v8i16 : BaseSIMDModifiedImmVectorShiftHalf<1, op, hw_cmode, V128,
6668 def v4i32 : BaseSIMDModifiedImmVectorShift<1, op, w_cmode, V128,
6680 def v8i16 : BaseSIMDModifiedImmVectorShiftHalfTied<1, op, hw_cmode, V128,
6682 [(set (v8i16 V128:$dst), (OpNode V128:$Rd,
6691 def v4i32 : BaseSIMDModifiedImmVectorShiftTied<1, op, w_cmode, V128,
6693 [(set (v4i32 V128:$dst), (OpNode V128:$Rd,
6807 V128, V128,
6810 [(set (v8f16 V128:$Rd),
6811 (OpNode (v8f16 V128:$Rn),
6822 V128, VectorIndexS,
6826 (v2f32 (AArch64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))))]> {
6833 V128, V128,
6834 V128, VectorIndexS,
6836 [(set (v4f32 V128:$Rd),
6837 (OpNode (v4f32 V128:$Rn),
6838 (v4f32 (AArch64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))))]> {
6845 V128, V128,
6846 V128, VectorIndexD,
6848 [(set (v2f64 V128:$Rd),
6849 (OpNode (v2f64 V128:$Rn),
6850 (v2f64 (AArch64duplane64 (v2f64 V128:$Rm), VectorIndexD:$idx))))]> {
6872 FPR32Op, FPR32Op, V128, VectorIndexS,
6876 (f32 (vector_extract (v4f32 V128:$Rm),
6884 FPR64Op, FPR64Op, V128, VectorIndexD,
6888 (f64 (vector_extract (v2f64 V128:$Rm),
6899 (AArch64duplane32 (v4f32 V128:$Rm),
6902 V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6910 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6911 (AArch64duplane32 (v4f32 V128:$Rm),
6914 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6915 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6917 (!cast<Instruction>(INST # "v4i32_indexed") V128:$Rd, V128:$Rn,
6921 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6922 (AArch64duplane64 (v2f64 V128:$Rm),
6925 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6926 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6928 (!cast<Instruction>(INST # "v2i64_indexed") V128:$Rd, V128:$Rn,
6933 (vector_extract (v4f32 V128:$Rm), VectorIndexS:$idx))),
6935 V128:$Rm, VectorIndexS:$idx)>;
6943 (vector_extract (v2f64 V128:$Rm), VectorIndexD:$idx))),
6945 V128:$Rm, VectorIndexD:$idx)>;
6960 V128, V128,
6971 V128, VectorIndexS,
6979 V128, V128,
6980 V128, VectorIndexS,
6988 V128, V128,
6989 V128, VectorIndexD,
7008 FPR32Op, FPR32Op, V128, VectorIndexS,
7016 FPR64Op, FPR64Op, V128, VectorIndexD,
7039 V128, V128,
7042 [(set (v8i16 V128:$Rd),
7043 (OpNode (v8i16 V128:$Rn),
7053 V128, VectorIndexS,
7057 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
7064 V128, V128,
7065 V128, VectorIndexS,
7067 [(set (v4i32 V128:$Rd),
7068 (OpNode (v4i32 V128:$Rn),
7069 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
7085 FPR32Op, FPR32Op, V128, VectorIndexS,
7089 (i32 (vector_extract (v4i32 V128:$Rm),
7113 V128, V128,
7116 [(set (v8i16 V128:$Rd),
7117 (OpNode (v8i16 V128:$Rn),
7127 V128, VectorIndexS,
7131 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
7138 V128, V128,
7139 V128, VectorIndexS,
7141 [(set (v4i32 V128:$Rd),
7142 (OpNode (v4i32 V128:$Rn),
7143 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
7165 V128, V128,
7168 [(set (v8i16 V128:$dst),
7169 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
7179 V128, VectorIndexS,
7183 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
7190 V128, V128,
7191 V128, VectorIndexS,
7193 [(set (v4i32 V128:$dst),
7194 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
7195 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
7205 V128, V64,
7208 [(set (v4i32 V128:$Rd),
7218 V128, V128,
7221 [(set (v4i32 V128:$Rd),
7222 (OpNode (extract_high_v8i16 V128:$Rn),
7233 V128, V64,
7234 V128, VectorIndexS,
7236 [(set (v2i64 V128:$Rd),
7238 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
7245 V128, V128,
7246 V128, VectorIndexS,
7248 [(set (v2i64 V128:$Rd),
7249 (OpNode (extract_high_v4i32 V128:$Rn),
7250 (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
7267 FPR64Op, FPR32Op, V128, VectorIndexS,
7278 V128, V64,
7281 [(set (v4i32 V128:$dst),
7282 (Accum (v4i32 V128:$Rd),
7308 V128, V128,
7311 [(set (v4i32 V128:$dst),
7312 (Accum (v4i32 V128:$Rd),
7314 (extract_high_v8i16 V128:$Rn),
7325 V128, V64,
7326 V128, VectorIndexS,
7328 [(set (v2i64 V128:$dst),
7329 (Accum (v2i64 V128:$Rd),
7332 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm),
7340 V128, V128,
7341 V128, VectorIndexS,
7343 [(set (v2i64 V128:$dst),
7344 (Accum (v2i64 V128:$Rd),
7346 (extract_high_v4i32 V128:$Rn),
7348 (AArch64duplane32 (v4i32 V128:$Rm),
7366 FPR64Op, FPR32Op, V128, VectorIndexS,
7372 (i32 (vector_extract (v4i32 V128:$Rm),
7385 V128, V64,
7388 [(set (v4i32 V128:$Rd),
7398 V128, V128,
7401 [(set (v4i32 V128:$Rd),
7402 (OpNode (extract_high_v8i16 V128:$Rn),
7413 V128, V64,
7414 V128, VectorIndexS,
7416 [(set (v2i64 V128:$Rd),
7418 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
7425 V128, V128,
7426 V128, VectorIndexS,
7428 [(set (v2i64 V128:$Rd),
7429 (OpNode (extract_high_v4i32 V128:$Rn),
7430 (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
7443 V128, V64,
7446 [(set (v4i32 V128:$dst),
7447 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn),
7456 V128, V128,
7459 [(set (v4i32 V128:$dst),
7460 (OpNode (v4i32 V128:$Rd),
7461 (extract_high_v8i16 V128:$Rn),
7471 V128, V64,
7472 V128, VectorIndexS,
7474 [(set (v2i64 V128:$dst),
7475 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn),
7476 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
7483 V128, V128,
7484 V128, VectorIndexS,
7486 [(set (v2i64 V128:$dst),
7487 (OpNode (v2i64 V128:$Rd),
7488 (extract_high_v4i32 V128:$Rn),
7489 (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
7739 V128, V128, vecshiftR16,
7741 [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (i32 imm:$imm)))]> {
7755 V128, V128, vecshiftR32,
7757 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (i32 imm:$imm)))]> {
7763 V128, V128, vecshiftR64,
7765 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (i32 imm:$imm)))]> {
7783 V128, V128, vecshiftR16,
7785 [(set (v8f16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (i32 imm:$imm)))]> {
7800 V128, V128, vecshiftR32,
7802 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (i32 imm:$imm)))]> {
7808 V128, V128, vecshiftR64,
7810 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (i32 imm:$imm)))]> {
7819 V64, V128, vecshiftR16Narrow,
7821 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))]> {
7827 V128, V128, vecshiftR16Narrow,
7835 V64, V128, vecshiftR32Narrow,
7837 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))]> {
7843 V128, V128, vecshiftR32Narrow,
7851 V64, V128, vecshiftR64Narrow,
7853 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))]> {
7859 V128, V128, vecshiftR64Narrow,
7871 def : Pat<(concat_vectors (v8i8 V64:$Rd),(OpNode (v8i16 V128:$Rn),
7875 V128:$Rn, vecshiftR16Narrow:$imm)>;
7876 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn),
7880 V128:$Rn, vecshiftR32Narrow:$imm)>;
7881 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn),
7885 V128:$Rn, vecshiftR64Narrow:$imm)>;
7900 V128, V128, vecshiftL8,
7902 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
7918 V128, V128, vecshiftL16,
7920 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7936 V128, V128, vecshiftL32,
7938 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
7945 V128, V128, vecshiftL64,
7947 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
7966 V128, V128, vecshiftR8,
7968 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
7984 V128, V128, vecshiftR16,
7986 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
8002 V128, V128, vecshiftR32,
8004 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
8011 V128, V128, vecshiftR64,
8013 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
8033 V128, V128, vecshiftR8, asm, ".16b", ".16b",
8034 [(set (v16i8 V128:$dst),
8035 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
8051 V128, V128, vecshiftR16, asm, ".8h", ".8h",
8052 [(set (v8i16 V128:$dst),
8053 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
8069 V128, V128, vecshiftR32, asm, ".4s", ".4s",
8070 [(set (v4i32 V128:$dst),
8071 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
8078 V128, V128, vecshiftR64,
8079 asm, ".2d", ".2d", [(set (v2i64 V128:$dst),
8080 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
8100 V128, V128, vecshiftL8,
8102 [(set (v16i8 V128:$dst),
8103 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
8120 V128, V128, vecshiftL16,
8122 [(set (v8i16 V128:$dst),
8123 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
8140 V128, V128, vecshiftL32,
8142 [(set (v4i32 V128:$dst),
8143 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
8150 V128, V128, vecshiftL64,
8152 [(set (v2i64 V128:$dst),
8153 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
8163 V128, V64, vecshiftL8, asm, ".8h", ".8b",
8164 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), vecshiftL8:$imm))]> {
8170 V128, V128, vecshiftL8,
8172 [(set (v8i16 V128:$Rd),
8173 (OpNode (extract_high_v16i8 V128:$Rn), vecshiftL8:$imm))]> {
8179 V128, V64, vecshiftL16, asm, ".4s", ".4h",
8180 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), vecshiftL16:$imm))]> {
8186 V128, V128, vecshiftL16,
8188 [(set (v4i32 V128:$Rd),
8189 (OpNode (extract_high_v8i16 V128:$Rn), vecshiftL16:$imm))]> {
8196 V128, V64, vecshiftL32, asm, ".2d", ".2s",
8197 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), vecshiftL32:$imm))]> {
8203 V128, V128, vecshiftL32,
8205 [(set (v2i64 V128:$Rd),
8206 (OpNode (extract_high_v4i32 V128:$Rn), vecshiftL32:$imm))]> {
9081 def v8i16 : BaseSIMDThreeSameVectorTiedR0<1, U, 0b01, opc, V128, asm, ".8h",
9082 [(set (v8i16 V128:$dst),
9083 (Accum (v8i16 V128:$Rd),
9084 (v8i16 (int_aarch64_neon_sqrdmulh (v8i16 V128:$Rn),
9085 (v8i16 V128:$Rm)))))]>;
9091 def v4i32 : BaseSIMDThreeSameVectorTiedR0<1, U, 0b10, opc, V128, asm, ".4s",
9092 [(set (v4i32 V128:$dst),
9093 (Accum (v4i32 V128:$Rd),
9094 (v4i32 (int_aarch64_neon_sqrdmulh (v4i32 V128:$Rn),
9095 (v4i32 V128:$Rm)))))]>;
9116 V128, V128, V128_lo, VectorIndexH,
9118 [(set (v8i16 V128:$dst),
9119 (Accum (v8i16 V128:$Rd),
9121 (v8i16 V128:$Rn),
9131 V64, V64, V128, VectorIndexS,
9137 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm),
9155 (v4i32 V128:$Rm),
9165 V128:$Rm,
9170 V128, V128, V128, VectorIndexS,
9172 [(set (v4i32 V128:$dst),
9173 (Accum (v4i32 V128:$Rd),
9175 (v4i32 V128:$Rn),
9176 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
9188 (v4i32 V128:$Rn),
9190 (v4i32 V128:$Rm),
9198 V128:$Rn,
9199 V128:$Rm,
9214 FPR32Op, FPR32Op, V128, VectorIndexS,
9220 (i32 (vector_extract (v4i32 V128:$Rm),
9249 : AESBase<opc, asm, (outs V128:$Rd), (ins V128:$Rn), "",
9250 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
9253 : AESBase<opc, asm, (outs V128:$dst), (ins V128:$Rd, V128:$Rn),
9255 [(set (v16i8 V128:$dst),
9256 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
9279 (ins FPR128:$Rd, FPR32:$Rn, V128:$Rm),
9282 (v4i32 V128:$Rm)))]>;
9285 : SHA3OpTiedInst<opc, asm, ".4s", (outs V128:$dst),
9286 (ins V128:$Rd, V128:$Rn, V128:$Rm),
9287 [(set (v4i32 V128:$dst),
9288 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
9289 (v4i32 V128:$Rm)))]>;
9293 (ins FPR128:$Rd, FPR128:$Rn, V128:$Rm),
9296 (v4i32 V128:$Rm)))]>;
9315 : SHA2OpInst<opc, asm, ".4s", "$Rd = $dst", (outs V128:$dst),
9316 (ins V128:$Rd, V128:$Rn),
9317 [(set (v4i32 V128:$dst),
9318 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;