42 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {  in getCalleeSavedRegs()
43   assert(MF && "Invalid MachineFunction pointer.");  in getCalleeSavedRegs()
44   if (MF->getFunction()->getCallingConv() == CallingConv::GHC)  in getCalleeSavedRegs()
48   if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg)  in getCalleeSavedRegs()
50   if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS)  in getCalleeSavedRegs()
51     return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() ?  in getCalleeSavedRegs()
59     const MachineFunction *MF) const {  in getCalleeSavedRegsViaCopy()
60   assert(MF && "Invalid MachineFunction pointer.");  in getCalleeSavedRegsViaCopy()
61   if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&  in getCalleeSavedRegsViaCopy()
62       MF->getInfo<AArch64FunctionInfo>()->isSplitCSR())  in getCalleeSavedRegsViaCopy()
68 AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,  in getCallPreservedMask()  argument
90 AArch64RegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,  in getThisReturnPreservedMask()  argument
104 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {  in getReservedRegs()
105   const AArch64FrameLowering *TFI = getFrameLowering(MF);  in getReservedRegs()
114   if (TFI->hasFP(MF) || TT.isOSDarwin()) {  in getReservedRegs()
119   if (MF.getSubtarget<AArch64Subtarget>().isX18Reserved()) {  in getReservedRegs()
124   if (hasBasePointer(MF)) {  in getReservedRegs()
132 bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF,  in isReservedReg()  argument
134   const AArch64FrameLowering *TFI = getFrameLowering(MF);  in isReservedReg()
146     return MF.getSubtarget<AArch64Subtarget>().isX18Reserved();  in isReservedReg()
149     return TFI->hasFP(MF) || TT.isOSDarwin();  in isReservedReg()
152     return hasBasePointer(MF);  in isReservedReg()
159 AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF,  in getPointerRegClass()  argument
173 bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const {  in hasBasePointer()
174   const MachineFrameInfo *MFI = MF.getFrameInfo();  in hasBasePointer()
184     if (needsStackRealignment(MF))  in hasBasePointer()
202 AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {  in getFrameRegister()
203   const AArch64FrameLowering *TFI = getFrameLowering(MF);  in getFrameRegister()
204   return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP;  in getFrameRegister()
208     const MachineFunction &MF) const {  in requiresRegisterScavenging()
213     const MachineFunction &MF) const {  in requiresVirtualBaseRegisters()
218 AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {  in useFPForScavengingIndex()
219   const MachineFrameInfo *MFI = MF.getFrameInfo();  in useFPForScavengingIndex()
223   return MFI->hasVarSizedObjects() && !hasBasePointer(MF);  in useFPForScavengingIndex()
227     const MachineFunction &MF) const {  in requiresFrameIndexScavenging()
232 AArch64RegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {  in cannotEliminateFrame()
233   const MachineFrameInfo *MFI = MF.getFrameInfo();  in cannotEliminateFrame()
235   if (MFI->hasCalls() || (MF.getTarget().Options.DisableFramePointerElim(MF) &&  in cannotEliminateFrame()
268   MachineFunction &MF = *MI->getParent()->getParent();  in needsFrameBaseReg()  local
269   const AArch64FrameLowering *TFI = getFrameLowering(MF);  in needsFrameBaseReg()
270   MachineFrameInfo *MFI = MF.getFrameInfo();  in needsFrameBaseReg()
290   if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset))  in needsFrameBaseReg()
324   const MachineFunction &MF = *MBB->getParent();  in materializeFrameBaseRegister()  local
326       MF.getSubtarget<AArch64Subtarget>().getInstrInfo();  in materializeFrameBaseRegister()
329   MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));  in materializeFrameBaseRegister()
347   const MachineFunction *MF = MI.getParent()->getParent();  in resolveFrameIndex()  local
349       MF->getSubtarget<AArch64Subtarget>().getInstrInfo();  in resolveFrameIndex()
362   MachineFunction &MF = *MBB.getParent();  in eliminateFrameIndex()  local
364       MF.getSubtarget<AArch64Subtarget>().getInstrInfo();  in eliminateFrameIndex()
365   const AArch64FrameLowering *TFI = getFrameLowering(MF);  in eliminateFrameIndex()
374     Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,  in eliminateFrameIndex()
383   Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg);  in eliminateFrameIndex()
394       MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass);  in eliminateFrameIndex()
402                                                   MachineFunction &MF) const {  in getRegPressureLimit()
403   const AArch64FrameLowering *TFI = getFrameLowering(MF);  in getRegPressureLimit()
417               - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP  in getRegPressureLimit()
418               - MF.getSubtarget<AArch64Subtarget>()  in getRegPressureLimit()
420               - hasBasePointer(MF);  // X19  in getRegPressureLimit()