Lines Matching refs:ins
641 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
665 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
666 SOP1 <outs, ins, "", pattern>,
672 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
673 SOP1 <outs, ins, asm, []>,
680 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
681 SOP1 <outs, ins, asm, []>,
688 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
691 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
693 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
695 def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
700 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
705 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
711 def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
713 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
718 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
726 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
728 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
733 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
741 op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
745 class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
746 SOP2<outs, ins, "", pattern>,
759 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
760 SOP2<outs, ins, asm, []>,
766 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
767 SOP2<outs, ins, asm, []>,
773 multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
776 def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
778 def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
780 def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
785 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
790 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
795 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
801 op, (outs), (ins rc:$src0, rc:$src1),
812 class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
813 SOPK <outs, ins, "", pattern>,
819 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
820 SOPK <outs, ins, asm, []>,
827 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
828 SOPK <outs, ins, asm, []>,
835 multiclass SOPK_m <sopk op, string opName, dag outs, dag ins, string opAsm,
837 def "" : SOPK_Pseudo <opName, outs, ins, []>;
839 def _si : SOPK_Real_si <op, opName, outs, ins, asm>;
841 def _vi : SOPK_Real_vi <op, opName, outs, ins, asm>;
846 def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
849 def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
852 def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
858 (ins SReg_32:$src0, u16imm:$src1), pattern> {
864 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16"> {
869 (ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16"> {
875 op, opName, (outs SReg_32:$sdst), (ins SReg_32:$src0, u16imm:$simm16),
879 multiclass SOPK_IMM32 <sopk op, string opName, dag outs, dag ins,
882 def "" : SOPK_Pseudo <opName, outs, ins, []>;
884 def _si : SOPK <outs, ins, asm, []>,
891 def _vi : SOPK <outs, ins, asm, []>,
902 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
903 SMRD <outs, ins, "", pattern>,
909 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
911 SMRD <outs, ins, asm, []>,
917 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
919 SMRD <outs, ins, asm, pattern>,
925 multiclass SMRD_m <smrd op, string opName, bit imm, dag outs, dag ins,
928 def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
930 def _si : SMRD_Real_si <op.SI, opName, imm, outs, ins, asm>;
935 def _vi : SMRD_Real_vi <op.VI, opName, imm, outs, ins, asm>;
942 def "" : SMRD_Pseudo <opName, (outs), (ins), [(node)]>;
946 def _si : SMRD_Real_si <op.SI, opName, 0, (outs), (ins), opName>;
950 def _vi : SMRD_Real_vi <op.VI, opName, 0, (outs), (ins), opName>;
957 SMRD_Real_vi<op, opName, 0, (outs), (ins), opName, [(node)]> {
970 (ins baseClass:$sbase, smrd_offset:$offset),
975 (outs dstClass:$dst), (ins baseClass:$sbase, smrd_literal_offset:$offset),
982 (ins baseClass:$sbase, SReg_32:$soff),
1056 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
1057 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1058 (ins)));
1070 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
1074 (ins Src0RC:$src0)
1079 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
1084 (ins Src0RC:$src0, Src1RC:$src1)
1089 (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
1095 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
1216 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
1244 let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
1260 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
1261 let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
1267 field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
1271 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2);
1343 class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1344 VOP1Common <outs, ins, "", pattern>,
1355 class VOP1_Real_si <string opName, vop1 op, dag outs, dag ins, string asm> :
1356 VOP1<op.SI, outs, ins, asm, []>,
1361 class VOP1_Real_vi <string opName, vop1 op, dag outs, dag ins, string asm> :
1362 VOP1<op.VI, outs, ins, asm, []>,
1385 class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1386 VOP2Common <outs, ins, "", pattern>,
1394 class VOP2_Real_si <string opName, vop2 op, dag outs, dag ins, string asm> :
1395 VOP2 <op.SI, outs, ins, opName#asm, []>,
1400 class VOP2_Real_vi <string opName, vop2 op, dag outs, dag ins, string asm> :
1401 VOP2 <op.VI, outs, ins, opName#asm, []>,
1449 class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
1450 VOP3Common <outs, ins, "", pattern>,
1461 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1462 VOP3Common <outs, ins, asm, []>,
1468 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1469 VOP3Common <outs, ins, asm, []>,
1475 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> :
1476 VOP3Common <outs, ins, asm, []>,
1482 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
1483 VOP3Common <outs, ins, asm, []>,
1489 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
1492 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1494 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1498 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1504 multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
1507 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1509 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1512 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1516 multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm,
1519 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1521 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1526 multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm,
1530 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1533 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1536 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1540 multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm,
1544 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1547 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1555 multiclass VOP3b_2_3_m <vop op, dag outs, dag ins, string asm,
1558 def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
1560 def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>,
1563 def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>,
1567 multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
1572 def "" : VOP3_Pseudo <outs, ins, pattern, opName>,
1578 def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
1584 def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>,
1592 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
1595 def "" : VOPAnyCommon <outs, ins, "", pattern>,
1599 def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
1604 def _vi : VOP3Common <outs, ins, asm, []>,
1753 class VOPC_Pseudo <dag ins, list<dag> pattern, string opName> :
1754 VOPCCommon <ins, "", pattern>,
1761 multiclass VOPC_m <vopc op, dag ins, string op_asm, list<dag> pattern,
1766 def "" : VOPC_Pseudo <ins, pattern, opName> {
1772 def _si : VOPC<op.SI, ins, asm, []>,
1782 def _vi : VOPC<op.VI, ins, asm, []>,
1875 multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm,
1877 op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods
1927 (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
1963 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1964 VINTRPCommon <outs, ins, "", pattern>,
1970 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1972 VINTRPCommon <outs, ins, asm, []>,
1976 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1978 VINTRPCommon <outs, ins, asm, []>,
1982 multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
1984 def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;
1986 def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>;
1988 def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;
1995 class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1996 DS <outs, ins, "", pattern>,
2002 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
2003 DS <outs, ins, asm, []>,
2009 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
2010 DS <outs, ins, asm, []>,
2014 class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
2015 DS_Real_si <op,opName, outs, ins, asm> {
2024 class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
2025 DS_Real_vi <op, opName, outs, ins, asm> {
2035 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds),
2038 def "" : DS_Pseudo <opName, outs, ins, []>;
2041 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2042 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2048 dag ins = (ins VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
2052 def "" : DS_Pseudo <opName, outs, ins, []>;
2055 def _si : DS_Real_si <op, opName, outs, ins, asm>;
2056 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
2062 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds),
2065 def "" : DS_Pseudo <opName, outs, ins, []>,
2069 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2070 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2076 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
2080 def "" : DS_Pseudo <opName, outs, ins, []>;
2083 def _si : DS_Real_si <op, opName, outs, ins, asm>;
2084 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
2091 dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds),
2095 def "" : DS_Pseudo <opName, outs, ins, []>,
2099 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2100 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2106 string noRetOp = "", dag ins,
2111 def "" : DS_Pseudo <opName, outs, ins, []>,
2114 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2115 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2122 (ins VGPR_32:$addr, src:$data0, src:$data1,
2129 dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1,
2133 def "" : DS_Pseudo <opName, outs, ins, []>,
2137 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2138 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2144 dag ins = (ins ds_offset:$offset, gds:$gds),
2148 def "" : DS_Pseudo <opName, outs, ins, []>;
2151 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2152 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2159 dag ins = (ins VGPR_32:$addr, ds_offset_gds:$offset),
2162 def "" : DS_Pseudo <opName, outs, ins, []>;
2165 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2166 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2172 dag ins = (ins VGPR_32:$addr),
2175 def "" : DS_Pseudo <opName, outs, ins, []>;
2178 def _si : DS_Real_si <op, opName, outs, ins, asm>;
2179 def _vi : DS_Real_vi <op, opName, outs, ins, asm>;
2185 dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds),
2189 def "" : DS_Pseudo <opName, outs, ins, []>;
2192 def _si : DS_Off16_Real_si <op, opName, outs, ins, asm>;
2193 def _vi : DS_Off16_Real_vi <op, opName, outs, ins, asm>;
2202 class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
2203 MTBUF <outs, ins, "", pattern>,
2209 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
2211 MTBUF <outs, ins, asm, []>,
2215 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
2216 MTBUF <outs, ins, asm, []>,
2220 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
2223 def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
2225 def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
2227 def _vi : MTBUF_Real_vi <{0, op{2}, op{1}, op{0}}, opName, outs, ins, asm>;
2236 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
2250 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
2270 class MUBUF_si <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
2271 MUBUF <outs, ins, asm, pattern>, MUBUFe <op> {
2277 class MUBUF_vi <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
2278 MUBUF <outs, ins, asm, pattern>, MUBUFe_vi <op> {
2287 class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
2288 MUBUF <outs, ins, "", pattern>,
2303 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
2305 MUBUF <outs, ins, asm, []>,
2311 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
2313 MUBUF <outs, ins, asm, []>,
2319 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
2322 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2326 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2329 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2333 dag ins, string asm, list<dag> pattern> {
2335 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2339 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2346 multiclass MUBUFAtomicOffset_m <mubuf op, string opName, dag outs, dag ins,
2349 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2355 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2358 def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>;
2362 multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins,
2365 def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
2370 def _si : MUBUF_Real_si <op, opName, outs, ins, asm>;
2387 (ins rc:$vdata, VReg_64:$vaddr, SReg_128:$srsrc,
2394 (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset,
2406 (ins rc:$vdata_in, VReg_64:$vaddr, SReg_128:$srsrc,
2416 (ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset,
2438 (ins SReg_128:$srsrc, SCSrc_32:$soffset,
2448 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2456 (ins VGPR_32:$vaddr, SReg_128:$srsrc,
2464 (ins VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2471 (ins VReg_64:$vaddr, SReg_128:$srsrc,
2488 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2496 (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset,
2505 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2514 (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2522 … (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2529 (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc,
2546 def "" : MUBUF_Pseudo <opName, (outs), (ins), [(node)]>;
2552 def _si : MUBUF_Real_si <op, opName, (outs), (ins), opName>;
2555 def _vi : MUBUF_Real_vi <op, opName, (outs), (ins), opName>;
2562 (ins VReg_64:$addr, glc_flat:$glc, slc_flat:$slc, tfe_flat:$tfe),
2569 FLAT <op, (outs), (ins vdataClass:$data, VReg_64:$addr,
2586 (ins VReg_64:$addr, data_rc:$data, slc_flat_atomic:$slc,
2595 (ins VReg_64:$addr, data_rc:$data, slc_flat_atomic:$slc,
2615 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2650 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
2696 (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,