Lines Matching refs:vdata

104      SDTCisVT<1, iAny>,   // vdata(VGPR)
2236   (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
2239   opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
2387         (ins rc:$vdata, VReg_64:$vaddr, SReg_128:$srsrc,
2389         name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0
2394         (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset,
2396         name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0
2401     let glc = 1, Constraints = "$vdata = $vdata_in",
2405         op, name#"_rtn_addr64", (outs rc:$vdata),
2408         name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc",
2409         [(set vt:$vdata,
2415         op, name#"_rtn_offset", (outs rc:$vdata),
2418         name#" $vdata, $srsrc, $soffset"#"$offset"#" glc$slc",
2419         [(set vt:$vdata,
2437       defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata),
2440                            name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2441                            [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
2447       defm _OFFEN  : MUBUF_m <op, name#"_offen", (outs regClass:$vdata),
2451 …                name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2455       defm _IDXEN  : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata),
2459 …                name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2463       defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata),
2466 …          name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2470       defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata),
2474                            name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#
2476                            [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc,
2488                     (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2491                     name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
2496                               (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset,
2498                               name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
2499                               [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
2505                              (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2508                              name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
2514                            (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc,
2517 …                name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2522 …                        (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset,
2524 …          name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
2529                                     (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc,
2533                                     name#" $vdata, $vaddr, $srsrc, $soffset addr64"#
2535                                     [(st store_vt:$vdata,
2550         vdata = 0, srsrc = 0, slc = 0, tfe = 0, soffset = 0 in {
2614   (outs dst_rc:$vdata),
2618   asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2649   (outs dst_rc:$vdata),
2653   asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
2695   (outs dst_rc:$vdata),
2699   asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"