97     Subtarget(STI) {  in ARMBaseInstrInfo()
122   if (Subtarget.isThumb2() || Subtarget.hasVFP2())  in CreateTargetPostRAHazardRecognizer()
662                                     const ARMSubtarget &Subtarget) const {  in copyFromCPSR()
663   unsigned Opc = Subtarget.isThumb()  in copyFromCPSR()
664                      ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR)  in copyFromCPSR()
672   if (Subtarget.isMClass())  in copyFromCPSR()
683                                   const ARMSubtarget &Subtarget) const {  in copyToCPSR()
684   unsigned Opc = Subtarget.isThumb()  in copyToCPSR()
685                      ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR)  in copyToCPSR()
690   if (Subtarget.isMClass())  in copyToCPSR()
725   else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && !Subtarget.isFPOnlySP())  in copyPhysReg()
767     Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr;  in copyPhysReg()
785   } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.isFPOnlySP()) {  in copyPhysReg()
790     copyFromCPSR(MBB, I, DestReg, KillSrc, Subtarget);  in copyPhysReg()
793     copyToCPSR(MBB, I, SrcReg, KillSrc, Subtarget);  in copyPhysReg()
879         if (Subtarget.hasV5TEOps()) {  in storeRegToStackSlot()
1067       if (Subtarget.hasV5TEOps()) {  in loadRegFromStackSlot()
1225   bool isThumb1 = Subtarget.isThumb1Only();  in expandMEMCPY()
1226   bool isThumb2 = Subtarget.isThumb2();  in expandMEMCPY()
1227   const ARMBaseInstrInfo *TII = Subtarget.getInstrInfo();  in expandMEMCPY()
1298   if (!WidenVMOVS || !MI->isCopy() || Subtarget.isCortexA15() ||  in expandPostRAPseudo()
1299       Subtarget.isFPOnlySP())  in expandPostRAPseudo()
1549   if (Subtarget.isThumb1Only()) return false;  in areLoadsFromSameBasePtr()
1630   if (Subtarget.isThumb1Only()) return false;  in shouldScheduleLoadsNear()
1737   UnpredCost += Subtarget.getMispredictionPenalty() * ScalingUpFactor / 10;  in isProfitableToIfCvt()
1760   UnpredCost += Subtarget.getMispredictionPenalty() * ScalingUpFactor / 10;  in isProfitableToIfCvt()
1770   return Subtarget.isSwift();  in isProfitableToUnpredicate()
2032 bool llvm::tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,  in tryFoldSPUpdateIntoPushPop()  argument
3016     if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore()))  in getNumMicroOps()
3089     if (Subtarget.isSwift()) {  in getNumMicroOps()
3124     } else if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {  in getNumMicroOps()
3133     } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {  in getNumMicroOps()
3161   if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {  in getVLDMDefCycle()
3166   } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {  in getVLDMDefCycle()
3202   if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {  in getLDMDefCycle()
3210   } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {  in getLDMDefCycle()
3236   if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {  in getVSTMUseCycle()
3241   } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {  in getVSTMUseCycle()
3276   if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {  in getSTMUseCycle()
3282   } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {  in getSTMUseCycle()
3462 static int adjustDefLatency(const ARMSubtarget &Subtarget,  in adjustDefLatency()  argument
3466   if (Subtarget.isCortexA8() || Subtarget.isLikeA9() || Subtarget.isCortexA7()) {  in adjustDefLatency()
3491   } else if (Subtarget.isSwift()) {  in adjustDefLatency()
3524   if (DefAlign < 8 && Subtarget.isLikeA9()) {  in adjustDefLatency()
3682       return Subtarget.isLikeA9() ? 1 : 20;  in getOperandLatency()
3696     if (Latency > 0 && Subtarget.isThumb2()) {  in getOperandLatency()
3724   Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);  in getOperandLatency()
3749     if (Subtarget.isLikeA9() || Subtarget.isSwift())  in getOperandLatency()
3766       (Subtarget.isCortexA8() || Subtarget.isLikeA9() ||  in getOperandLatency()
3767        Subtarget.isCortexA7())) {  in getOperandLatency()
3794   } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) {  in getOperandLatency()
3823   if (DefAlign < 8 && Subtarget.isLikeA9())  in getOperandLatency()
4010   int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign);  in getInstrLatency()
4042   if (Subtarget.isCortexA8() &&  in hasHighOperandLatency()
4097   if (Subtarget.GVIsIndirectSymbol(GV, RM)) {  in expandLoadStackGuardBase()
4152   if (Subtarget.hasNEON()) {  in getExecutionDomain()
4160     if (Subtarget.isCortexA9() && !isPredicated(MI) &&  in getExecutionDomain()
4173   if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())  in getExecutionDomain()
4258       assert(Subtarget.hasNEON() && "VORRd requires NEON");  in setExecutionDomain()
4454       !(Subtarget.isSwift() || Subtarget.isCortexA15()))  in getPartialRegUpdateClearance()
4547   return Subtarget.getFeatureBits()[ARM::HasV6KOps];  in hasNOP()