Lines Matching refs:VA
1440 CCValAssign VA = RVLocs[i]; in LowerCallResult() local
1445 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 && in LowerCallResult()
1452 if (VA.needsCustom()) { in LowerCallResult()
1454 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1458 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
1459 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1467 if (VA.getLocVT() == MVT::v2f64) { in LowerCallResult()
1472 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
1473 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1476 VA = RVLocs[++i]; // skip ahead to next loc in LowerCallResult()
1477 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1487 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), in LowerCallResult()
1493 switch (VA.getLocInfo()) { in LowerCallResult()
1497 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); in LowerCallResult()
1512 const CCValAssign &VA, in LowerMemOpCallTo() argument
1514 unsigned LocMemOffset = VA.getLocMemOffset(); in LowerMemOpCallTo()
1527 CCValAssign &VA, CCValAssign &NextVA, in PassF64ArgInRegs() argument
1535 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id))); in PassF64ArgInRegs()
1627 CCValAssign &VA = ArgLocs[i]; in LowerCall() local
1633 switch (VA.getLocInfo()) { in LowerCall()
1637 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
1640 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
1643 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
1646 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall()
1651 if (VA.needsCustom()) { in LowerCall()
1652 if (VA.getLocVT() == MVT::v2f64) { in LowerCall()
1659 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); in LowerCall()
1661 VA = ArgLocs[++i]; // skip ahead to next loc in LowerCall()
1662 if (VA.isRegLoc()) { in LowerCall()
1664 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); in LowerCall()
1666 assert(VA.isMemLoc()); in LowerCall()
1669 dl, DAG, VA, Flags)); in LowerCall()
1672 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i], in LowerCall()
1675 } else if (VA.isRegLoc()) { in LowerCall()
1677 assert(VA.getLocVT() == MVT::i32 && in LowerCall()
1683 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
1685 assert(VA.isMemLoc()); in LowerCall()
1721 unsigned LocMemOffset = VA.getLocMemOffset(); in LowerCall()
1737 assert(VA.isMemLoc()); in LowerCall()
1740 dl, DAG, VA, Flags)); in LowerCall()
2183 CCValAssign &VA = ArgLocs[i]; in IsEligibleForTailCallOptimization() local
2184 EVT RegVT = VA.getLocVT(); in IsEligibleForTailCallOptimization()
2187 if (VA.getLocInfo() == CCValAssign::Indirect) in IsEligibleForTailCallOptimization()
2189 if (VA.needsCustom()) { in IsEligibleForTailCallOptimization()
2194 if (!VA.isRegLoc()) in IsEligibleForTailCallOptimization()
2204 } else if (!VA.isRegLoc()) { in IsEligibleForTailCallOptimization()
2205 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, in IsEligibleForTailCallOptimization()
2291 CCValAssign &VA = RVLocs[i]; in LowerReturn() local
2292 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
2296 switch (VA.getLocInfo()) { in LowerReturn()
2300 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerReturn()
2304 if (VA.needsCustom()) { in LowerReturn()
2305 if (VA.getLocVT() == MVT::v2f64) { in LowerReturn()
2312 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
2316 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
2317 VA = RVLocs[++i]; // skip ahead to next loc in LowerReturn()
2318 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
2322 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
2323 VA = RVLocs[++i]; // skip ahead to next loc in LowerReturn()
2333 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
2337 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
2338 VA = RVLocs[++i]; // skip ahead to next loc in LowerReturn()
2339 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
2343 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); in LowerReturn()
2348 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
2937 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, in GetF64FormalArgument() argument
2950 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in GetF64FormalArgument()
3099 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments() local
3100 unsigned Index = VA.getValNo(); in LowerFormalArguments()
3105 assert(VA.isMemLoc() && "unexpected byval pointer in reg"); in LowerFormalArguments()
3126 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments() local
3127 if (Ins[VA.getValNo()].isOrigArg()) { in LowerFormalArguments()
3129 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx); in LowerFormalArguments()
3130 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex(); in LowerFormalArguments()
3133 if (VA.isRegLoc()) { in LowerFormalArguments()
3134 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
3136 if (VA.needsCustom()) { in LowerFormalArguments()
3139 if (VA.getLocVT() == MVT::v2f64) { in LowerFormalArguments()
3140 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i], in LowerFormalArguments()
3142 VA = ArgLocs[++i]; // skip ahead to next loc in LowerFormalArguments()
3144 if (VA.isMemLoc()) { in LowerFormalArguments()
3145 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true); in LowerFormalArguments()
3152 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], in LowerFormalArguments()
3163 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl); in LowerFormalArguments()
3181 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
3188 switch (VA.getLocInfo()) { in LowerFormalArguments()
3192 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
3196 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
3197 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
3201 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
3202 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
3211 assert(VA.isMemLoc()); in LowerFormalArguments()
3212 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered"); in LowerFormalArguments()
3214 int index = VA.getValNo(); in LowerFormalArguments()
3233 VA.getLocMemOffset(), Flags.getByValSize()); in LowerFormalArguments()
3237 unsigned FIOffset = VA.getLocMemOffset(); in LowerFormalArguments()
3238 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8, in LowerFormalArguments()
3244 VA.getValVT(), dl, Chain, FIN, in LowerFormalArguments()