Lines Matching refs:Rn
611 : PseudoVFPLdStM<(outs DPair:$dst), (ins GPR:$Rn),
613 [(set DPair:$dst, (v2f64 (load GPR:$Rn)))]>;
618 : PseudoVFPLdStM<(outs), (ins DPair:$src, GPR:$Rn),
620 [(store (v2f64 DPair:$src), GPR:$Rn)]>;
668 (ins AddrMode:$Rn), IIC_VLD1,
669 "vld1", Dt, "$Vd, $Rn", "", []> {
671 let Inst{4} = Rn{4};
676 (ins AddrMode:$Rn), IIC_VLD1x2,
677 "vld1", Dt, "$Vd, $Rn", "", []> {
679 let Inst{5-4} = Rn{5-4};
696 (ins AddrMode:$Rn), IIC_VLD1u,
697 "vld1", Dt, "$Vd, $Rn!",
698 "$Rn.addr = $wb", []> {
700 let Inst{4} = Rn{4};
704 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1u,
705 "vld1", Dt, "$Vd, $Rn, $Rm",
706 "$Rn.addr = $wb", []> {
707 let Inst{4} = Rn{4};
713 (ins AddrMode:$Rn), IIC_VLD1x2u,
714 "vld1", Dt, "$Vd, $Rn!",
715 "$Rn.addr = $wb", []> {
717 let Inst{5-4} = Rn{5-4};
721 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
722 "vld1", Dt, "$Vd, $Rn, $Rm",
723 "$Rn.addr = $wb", []> {
724 let Inst{5-4} = Rn{5-4};
741 (ins AddrMode:$Rn), IIC_VLD1x3, "vld1", Dt,
742 "$Vd, $Rn", "", []> {
744 let Inst{4} = Rn{4};
749 (ins AddrMode:$Rn), IIC_VLD1x2u,
750 "vld1", Dt, "$Vd, $Rn!",
751 "$Rn.addr = $wb", []> {
753 let Inst{4} = Rn{4};
757 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
758 "vld1", Dt, "$Vd, $Rn, $Rm",
759 "$Rn.addr = $wb", []> {
760 let Inst{4} = Rn{4};
782 (ins AddrMode:$Rn), IIC_VLD1x4, "vld1", Dt,
783 "$Vd, $Rn", "", []> {
785 let Inst{5-4} = Rn{5-4};
790 (ins AddrMode:$Rn), IIC_VLD1x2u,
791 "vld1", Dt, "$Vd, $Rn!",
792 "$Rn.addr = $wb", []> {
794 let Inst{5-4} = Rn{5-4};
798 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
799 "vld1", Dt, "$Vd, $Rn, $Rm",
800 "$Rn.addr = $wb", []> {
801 let Inst{5-4} = Rn{5-4};
824 (ins AddrMode:$Rn), itin,
825 "vld2", Dt, "$Vd, $Rn", "", []> {
827 let Inst{5-4} = Rn{5-4};
853 (ins AddrMode:$Rn), itin,
854 "vld2", Dt, "$Vd, $Rn!",
855 "$Rn.addr = $wb", []> {
857 let Inst{5-4} = Rn{5-4};
861 (ins AddrMode:$Rn, rGPR:$Rm), itin,
862 "vld2", Dt, "$Vd, $Rn, $Rm",
863 "$Rn.addr = $wb", []> {
864 let Inst{5-4} = Rn{5-4};
907 (ins addrmode6:$Rn), IIC_VLD3,
908 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
910 let Inst{4} = Rn{4};
926 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
927 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
928 "$Rn.addr = $wb", []> {
929 let Inst{4} = Rn{4};
966 (ins addrmode6:$Rn), IIC_VLD4,
967 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
969 let Inst{5-4} = Rn{5-4};
985 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
986 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
987 "$Rn.addr = $wb", []> {
988 let Inst{5-4} = Rn{5-4};
1054 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
1055 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1058 (i32 (LoadOp addrmode6:$Rn)),
1066 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
1067 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1070 (i32 (LoadOp addrmode6oneL32:$Rn)),
1086 let Inst{5-4} = Rn{5-4};
1090 let Inst{5-4} = Rn{5-4};
1109 (ins addrmode6:$Rn, am6offset:$Rm,
1111 "\\{$Vd[$lane]\\}, $Rn$Rm",
1112 "$src = $Vd, $Rn.addr = $wb", []> {
1121 let Inst{4} = Rn{4};
1125 let Inst{5} = Rn{4};
1126 let Inst{4} = Rn{4};
1136 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
1137 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
1140 let Inst{4} = Rn{4};
1172 (ins addrmode6:$Rn, am6offset:$Rm,
1174 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
1175 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
1176 let Inst{4} = Rn{4};
1207 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
1209 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
1244 (ins addrmode6:$Rn, am6offset:$Rm,
1247 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
1248 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
1281 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1283 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
1286 let Inst{4} = Rn{4};
1298 let Inst{5} = Rn{5};
1311 let Inst{5} = Rn{5};
1321 (ins addrmode6:$Rn, am6offset:$Rm,
1324 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
1325 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
1327 let Inst{4} = Rn{4};
1339 let Inst{5} = Rn{5};
1351 let Inst{5} = Rn{5};
1363 (ins AddrMode:$Rn),
1364 IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "",
1366 (Ty (NEONvdup (i32 (LoadOp AddrMode:$Rn)))))]> {
1368 let Inst{4} = Rn{4};
1384 (ins AddrMode:$Rn), IIC_VLD1dup,
1385 "vld1", Dt, "$Vd, $Rn", "",
1387 (Ty (NEONvdup (i32 (LoadOp AddrMode:$Rn)))))]> {
1389 let Inst{4} = Rn{4};
1408 (ins AddrMode:$Rn), IIC_VLD1dupu,
1409 "vld1", Dt, "$Vd, $Rn!",
1410 "$Rn.addr = $wb", []> {
1412 let Inst{4} = Rn{4};
1417 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1418 "vld1", Dt, "$Vd, $Rn, $Rm",
1419 "$Rn.addr = $wb", []> {
1420 let Inst{4} = Rn{4};
1427 (ins AddrMode:$Rn), IIC_VLD1dupu,
1428 "vld1", Dt, "$Vd, $Rn!",
1429 "$Rn.addr = $wb", []> {
1431 let Inst{4} = Rn{4};
1436 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1437 "vld1", Dt, "$Vd, $Rn, $Rm",
1438 "$Rn.addr = $wb", []> {
1439 let Inst{4} = Rn{4};
1455 (ins AddrMode:$Rn), IIC_VLD2dup,
1456 "vld2", Dt, "$Vd, $Rn", "", []> {
1458 let Inst{4} = Rn{4};
1484 (ins AddrMode:$Rn), IIC_VLD2dupu,
1485 "vld2", Dt, "$Vd, $Rn!",
1486 "$Rn.addr = $wb", []> {
1488 let Inst{4} = Rn{4};
1493 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD2dupu,
1494 "vld2", Dt, "$Vd, $Rn, $Rm",
1495 "$Rn.addr = $wb", []> {
1496 let Inst{4} = Rn{4};
1518 (ins addrmode6dup:$Rn), IIC_VLD3dup,
1519 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
1541 (ins AddrMode:$Rn, am6offset:$Rm), IIC_VLD3dupu,
1542 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1543 "$Rn.addr = $wb", []> {
1564 (ins addrmode6dup:$Rn), IIC_VLD4dup,
1565 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1567 let Inst{4} = Rn{4};
1573 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1582 def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1588 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
1589 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1590 "$Rn.addr = $wb", []> {
1591 let Inst{4} = Rn{4};
1597 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1601 def VLD4DUPq32_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1651 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins AddrMode:$Rn, VecListOneD:$Vd),
1652 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {
1654 let Inst{4} = Rn{4};
1658 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins AddrMode:$Rn, VecListDPair:$Vd),
1659 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> {
1661 let Inst{5-4} = Rn{5-4};
1678 (ins AddrMode:$Rn, VecListOneD:$Vd), IIC_VLD1u,
1679 "vst1", Dt, "$Vd, $Rn!",
1680 "$Rn.addr = $wb", []> {
1682 let Inst{4} = Rn{4};
1686 (ins AddrMode:$Rn, rGPR:$Rm, VecListOneD:$Vd),
1688 "vst1", Dt, "$Vd, $Rn, $Rm",
1689 "$Rn.addr = $wb", []> {
1690 let Inst{4} = Rn{4};
1696 (ins AddrMode:$Rn, VecListDPair:$Vd), IIC_VLD1x2u,
1697 "vst1", Dt, "$Vd, $Rn!",
1698 "$Rn.addr = $wb", []> {
1700 let Inst{5-4} = Rn{5-4};
1704 (ins AddrMode:$Rn, rGPR:$Rm, VecListDPair:$Vd),
1706 "vst1", Dt, "$Vd, $Rn, $Rm",
1707 "$Rn.addr = $wb", []> {
1708 let Inst{5-4} = Rn{5-4};
1726 (ins AddrMode:$Rn, VecListThreeD:$Vd),
1727 IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> {
1729 let Inst{4} = Rn{4};
1734 (ins AddrMode:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
1735 "vst1", Dt, "$Vd, $Rn!",
1736 "$Rn.addr = $wb", []> {
1738 let Inst{5-4} = Rn{5-4};
1742 (ins AddrMode:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
1744 "vst1", Dt, "$Vd, $Rn, $Rm",
1745 "$Rn.addr = $wb", []> {
1746 let Inst{5-4} = Rn{5-4};
1768 (ins AddrMode:$Rn, VecListFourD:$Vd),
1769 IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "",
1772 let Inst{5-4} = Rn{5-4};
1777 (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
1778 "vst1", Dt, "$Vd, $Rn!",
1779 "$Rn.addr = $wb", []> {
1781 let Inst{5-4} = Rn{5-4};
1785 (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1787 "vst1", Dt, "$Vd, $Rn, $Rm",
1788 "$Rn.addr = $wb", []> {
1789 let Inst{5-4} = Rn{5-4};
1811 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins AddrMode:$Rn, VdTy:$Vd),
1812 itin, "vst2", Dt, "$Vd, $Rn", "", []> {
1814 let Inst{5-4} = Rn{5-4};
1840 (ins AddrMode:$Rn, VdTy:$Vd), IIC_VLD1u,
1841 "vst2", Dt, "$Vd, $Rn!",
1842 "$Rn.addr = $wb", []> {
1844 let Inst{5-4} = Rn{5-4};
1848 (ins AddrMode:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
1849 "vst2", Dt, "$Vd, $Rn, $Rm",
1850 "$Rn.addr = $wb", []> {
1851 let Inst{5-4} = Rn{5-4};
1857 (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1u,
1858 "vst2", Dt, "$Vd, $Rn!",
1859 "$Rn.addr = $wb", []> {
1861 let Inst{5-4} = Rn{5-4};
1865 (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1867 "vst2", Dt, "$Vd, $Rn, $Rm",
1868 "$Rn.addr = $wb", []> {
1869 let Inst{5-4} = Rn{5-4};
1909 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1910 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1912 let Inst{4} = Rn{4};
1927 (ins addrmode6:$Rn, am6offset:$Rm,
1929 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1930 "$Rn.addr = $wb", []> {
1931 let Inst{4} = Rn{4};
1967 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1968 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1971 let Inst{5-4} = Rn{5-4};
1986 (ins addrmode6:$Rn, am6offset:$Rm,
1988 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1989 "$Rn.addr = $wb", []> {
1990 let Inst{5-4} = Rn{5-4};
2053 (ins AddrMode:$Rn, DPR:$Vd, nohash_imm:$lane),
2054 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
2055 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), AddrMode:$Rn)]> {
2072 let Inst{4} = Rn{4};
2078 let Inst{5-4} = Rn{5-4};
2094 (ins AdrMode:$Rn, am6offset:$Rm,
2096 "\\{$Vd[$lane]\\}, $Rn$Rm",
2097 "$Rn.addr = $wb",
2099 AdrMode:$Rn, am6offset:$Rm))]> {
2115 let Inst{4} = Rn{4};
2120 let Inst{5-4} = Rn{5-4};
2132 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
2133 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
2136 let Inst{4} = Rn{4};
2157 let Inst{4} = Rn{4};
2161 let Inst{4} = Rn{4};
2170 (ins addrmode6:$Rn, am6offset:$Rm,
2172 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm",
2173 "$Rn.addr = $wb", []> {
2174 let Inst{4} = Rn{4};
2205 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
2207 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
2240 (ins addrmode6:$Rn, am6offset:$Rm,
2243 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
2244 "$Rn.addr = $wb", []> {
2275 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2277 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
2280 let Inst{4} = Rn{4};
2292 let Inst{5} = Rn{5};
2305 let Inst{5} = Rn{5};
2314 (ins addrmode6:$Rn, am6offset:$Rm,
2317 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
2318 "$Rn.addr = $wb", []> {
2319 let Inst{4} = Rn{4};
2331 let Inst{5} = Rn{5};
2343 let Inst{5} = Rn{5};
4219 def : Pat<(v2f32 (fmul DPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
4220 (VMULslfd DPR:$Rn,
4223 def : Pat<(v4f32 (fmul QPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
4224 (VMULslfq QPR:$Rn,
5452 def : Pat<(v8i16 (NEONvshl (zext (v8i8 DPR:$Rn)), (i32 8))),
5453 (VSHLLi8 DPR:$Rn, 8)>;
5454 def : Pat<(v4i32 (NEONvshl (zext (v4i16 DPR:$Rn)), (i32 16))),
5455 (VSHLLi16 DPR:$Rn, 16)>;
5456 def : Pat<(v2i64 (NEONvshl (zext (v2i32 DPR:$Rn)), (i32 32))),
5457 (VSHLLi32 DPR:$Rn, 32)>;
5458 def : Pat<(v8i16 (NEONvshl (sext (v8i8 DPR:$Rn)), (i32 8))),
5459 (VSHLLi8 DPR:$Rn, 8)>;
5460 def : Pat<(v4i32 (NEONvshl (sext (v4i16 DPR:$Rn)), (i32 16))),
5461 (VSHLLi16 DPR:$Rn, 16)>;
5462 def : Pat<(v2i64 (NEONvshl (sext (v2i32 DPR:$Rn)), (i32 32))),
5463 (VSHLLi32 DPR:$Rn, 32)>;
5467 PatFrag<(ops node:$Rn, node:$amt),
5468 (trunc (NEONvshrs node:$Rn, node:$amt))>>;
6587 def : Pat<(i32 (int_arm_neon_sha1h i32:$Rn)),
6590 (f32 (COPY_TO_REGCLASS i32:$Rn, SPR)),
7133 def : VFP2InstAlias<"fmdhr${p} $Dd, $Rn",
7134 (VSETLNi32 DPR:$Dd, GPR:$Rn, 1, pred:$p)>;
7135 def : VFP2InstAlias<"fmdlr${p} $Dd, $Rn",
7136 (VSETLNi32 DPR:$Dd, GPR:$Rn, 0, pred:$p)>;