Lines Matching refs:lane
267 // Register list of one D register, with byte lane subscripting.
277 // ...with half-word lane subscripting.
287 // ...with word lane subscripting.
298 // Register list of two D registers with byte lane subscripting.
308 // ...with half-word lane subscripting.
318 // ...with word lane subscripting.
328 // Register list of two Q registers with half-word lane subscripting.
338 // ...with word lane subscripting.
350 // Register list of three D registers with byte lane subscripting.
360 // ...with half-word lane subscripting.
370 // ...with word lane subscripting.
380 // Register list of three Q registers with half-word lane subscripting.
390 // ...with word lane subscripting.
401 // Register list of four D registers with byte lane subscripting.
411 // ...with half-word lane subscripting.
421 // ...with word lane subscripting.
431 // Register list of four Q registers with half-word lane subscripting.
441 // ...with word lane subscripting.
1027 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1032 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
1035 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1040 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
1043 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1048 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
1050 // VLD1LN : Vector Load (single element to one lane)
1054 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
1055 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1059 imm:$lane))]> {
1066 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
1067 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1071 imm:$lane))]> {
1078 imm:$lane))];
1082 let Inst{7-5} = lane{2-0};
1085 let Inst{7-6} = lane{1-0};
1089 let Inst{7} = lane{0};
1098 (f32 (load addrmode6:$addr)), imm:$lane),
1099 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1101 (f32 (load addrmode6:$addr)), imm:$lane),
1102 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1110 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
1111 "\\{$Vd[$lane]\\}, $Rn$Rm",
1117 let Inst{7-5} = lane{2-0};
1120 let Inst{7-6} = lane{1-0};
1124 let Inst{7} = lane{0};
1133 // VLD2LN : Vector Load (single 2-element structure to one lane)
1136 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
1137 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
1145 let Inst{7-5} = lane{2-0};
1148 let Inst{7-6} = lane{1-0};
1151 let Inst{7} = lane{0};
1160 let Inst{7-6} = lane{1-0};
1163 let Inst{7} = lane{0};
1173 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
1174 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
1181 let Inst{7-5} = lane{2-0};
1184 let Inst{7-6} = lane{1-0};
1187 let Inst{7} = lane{0};
1195 let Inst{7-6} = lane{1-0};
1198 let Inst{7} = lane{0};
1204 // VLD3LN : Vector Load (single 3-element structure to one lane)
1208 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
1209 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
1216 let Inst{7-5} = lane{2-0};
1219 let Inst{7-6} = lane{1-0};
1222 let Inst{7} = lane{0};
1231 let Inst{7-6} = lane{1-0};
1234 let Inst{7} = lane{0};
1245 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1247 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
1254 let Inst{7-5} = lane{2-0};
1257 let Inst{7-6} = lane{1-0};
1260 let Inst{7} = lane{0};
1268 let Inst{7-6} = lane{1-0};
1271 let Inst{7} = lane{0};
1277 // VLD4LN : Vector Load (single 4-element structure to one lane)
1282 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
1283 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
1291 let Inst{7-5} = lane{2-0};
1294 let Inst{7-6} = lane{1-0};
1297 let Inst{7} = lane{0};
1307 let Inst{7-6} = lane{1-0};
1310 let Inst{7} = lane{0};
1322 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1324 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
1332 let Inst{7-5} = lane{2-0};
1335 let Inst{7-6} = lane{1-0};
1338 let Inst{7} = lane{0};
1347 let Inst{7-6} = lane{1-0};
1350 let Inst{7} = lane{0};
2028 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
2033 nohash_imm:$lane), itin, "$addr.addr = $wb">;
2035 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
2040 nohash_imm:$lane), itin, "$addr.addr = $wb">;
2042 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
2047 nohash_imm:$lane), itin, "$addr.addr = $wb">;
2049 // VST1LN : Vector Store (single element from one lane)
2053 (ins AddrMode:$Rn, DPR:$Vd, nohash_imm:$lane),
2054 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
2055 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), AddrMode:$Rn)]> {
2061 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
2067 let Inst{7-5} = lane{2-0};
2071 let Inst{7-6} = lane{1-0};
2077 let Inst{7} = lane{0};
2085 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
2086 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
2087 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
2088 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
2095 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
2096 "\\{$Vd[$lane]\\}, $Rn$Rm",
2098 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
2104 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
2110 let Inst{7-5} = lane{2-0};
2114 let Inst{7-6} = lane{1-0};
2119 let Inst{7} = lane{0};
2129 // VST2LN : Vector Store (single 2-element structure from one lane)
2132 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
2133 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
2141 let Inst{7-5} = lane{2-0};
2144 let Inst{7-6} = lane{1-0};
2147 let Inst{7} = lane{0};
2156 let Inst{7-6} = lane{1-0};
2160 let Inst{7} = lane{0};
2171 DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
2172 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm",
2179 let Inst{7-5} = lane{2-0};
2182 let Inst{7-6} = lane{1-0};
2185 let Inst{7} = lane{0};
2193 let Inst{7-6} = lane{1-0};
2196 let Inst{7} = lane{0};
2202 // VST3LN : Vector Store (single 3-element structure from one lane)
2206 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
2207 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
2213 let Inst{7-5} = lane{2-0};
2216 let Inst{7-6} = lane{1-0};
2219 let Inst{7} = lane{0};
2228 let Inst{7-6} = lane{1-0};
2231 let Inst{7} = lane{0};
2241 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
2243 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
2249 let Inst{7-5} = lane{2-0};
2252 let Inst{7-6} = lane{1-0};
2255 let Inst{7} = lane{0};
2263 let Inst{7-6} = lane{1-0};
2266 let Inst{7} = lane{0};
2272 // VST4LN : Vector Store (single 4-element structure from one lane)
2276 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
2277 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
2285 let Inst{7-5} = lane{2-0};
2288 let Inst{7-6} = lane{1-0};
2291 let Inst{7} = lane{0};
2301 let Inst{7-6} = lane{1-0};
2304 let Inst{7} = lane{0};
2315 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
2317 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
2324 let Inst{7-5} = lane{2-0};
2327 let Inst{7-6} = lane{1-0};
2330 let Inst{7} = lane{0};
2339 let Inst{7-6} = lane{1-0};
2342 let Inst{7} = lane{0};
2417 // Translate lane numbers from Q registers to D subregs.
2574 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2575 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2578 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
2586 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2587 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
2590 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2622 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2623 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2627 imm:$lane)))))]> {
2635 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2636 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
2640 imm:$lane)))))]> {
2670 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2671 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2675 imm:$lane)))))]> {
2682 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2683 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2686 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2737 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2738 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2742 imm:$lane)))))]> {
2749 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2750 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2754 imm:$lane)))))]> {
2783 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2785 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2790 imm:$lane)))))))]>;
2796 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2798 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2803 imm:$lane)))))))]>;
2818 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2820 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2825 imm:$lane)))))))]>;
2832 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2834 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2839 imm:$lane)))))))]>;
2892 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2894 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2899 imm:$lane))))))]>;
2904 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2906 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2911 imm:$lane))))))]>;
2940 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2942 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2947 imm:$lane)))))]>;
2953 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2955 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2960 imm:$lane)))))]>;
2988 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2989 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2992 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2997 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2998 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3001 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
3053 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
3054 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3058 imm:$lane)))))]>;
3063 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
3064 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3068 imm:$lane)))))]>;
4200 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
4203 (DSubReg_i16_reg imm:$lane))),
4204 (SubReg_i16_lane imm:$lane)))>;
4206 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
4209 (DSubReg_i32_reg imm:$lane))),
4210 (SubReg_i32_lane imm:$lane)))>;
4212 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
4215 (DSubReg_i32_reg imm:$lane))),
4216 (SubReg_i32_lane imm:$lane)))>;
4238 imm:$lane)))),
4241 (DSubReg_i16_reg imm:$lane))),
4242 (SubReg_i16_lane imm:$lane)))>;
4245 imm:$lane)))),
4248 (DSubReg_i32_reg imm:$lane))),
4249 (SubReg_i32_lane imm:$lane)))>;
4260 imm:$lane)))),
4263 (DSubReg_i16_reg imm:$lane))),
4264 (SubReg_i16_lane imm:$lane)))>;
4267 imm:$lane)))),
4270 (DSubReg_i32_reg imm:$lane))),
4271 (SubReg_i32_lane imm:$lane)))>;
4329 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4332 (DSubReg_i16_reg imm:$lane))),
4333 (SubReg_i16_lane imm:$lane)))>;
4337 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4340 (DSubReg_i32_reg imm:$lane))),
4341 (SubReg_i32_lane imm:$lane)))>;
4345 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4349 (DSubReg_i32_reg imm:$lane))),
4350 (SubReg_i32_lane imm:$lane)))>,
4398 imm:$lane)))))),
4400 imm:$lane))>;
4406 imm:$lane)))))),
4408 imm:$lane))>;
4414 imm:$lane)))))),
4419 (DSubReg_i16_reg imm:$lane))),
4420 (SubReg_i16_lane imm:$lane)))>;
4426 imm:$lane)))))),
4431 (DSubReg_i32_reg imm:$lane))),
4432 (SubReg_i32_lane imm:$lane)))>;
4468 imm:$lane)))))),
4469 (v4i16 (VQRDMLSHslv4i16 DPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane))>;
4475 imm:$lane)))))),
4477 imm:$lane))>;
4483 imm:$lane)))))),
4488 (DSubReg_i16_reg imm:$lane))),
4489 (SubReg_i16_lane imm:$lane)))>;
4495 imm:$lane)))))),
4500 (DSubReg_i32_reg imm:$lane))),
4501 (SubReg_i32_lane imm:$lane)))>;
4519 imm:$lane)))))),
4520 (VQDMLALslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4524 imm:$lane)))))),
4525 (VQDMLALslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4559 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4562 (DSubReg_i16_reg imm:$lane))),
4563 (SubReg_i16_lane imm:$lane)))>;
4567 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4570 (DSubReg_i32_reg imm:$lane))),
4571 (SubReg_i32_lane imm:$lane)))>;
4575 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4578 (DSubReg_i32_reg imm:$lane))),
4579 (SubReg_i32_lane imm:$lane)))>,
4607 imm:$lane)))))),
4608 (VQDMLSLslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4612 imm:$lane)))))),
4613 (VQDMLSLslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
5801 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
5802 IIC_VMOVSI, "vmov", "s8", "$R, $V$lane",
5804 imm:$lane))]> {
5805 let Inst{21} = lane{2};
5806 let Inst{6-5} = lane{1-0};
5809 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
5810 IIC_VMOVSI, "vmov", "s16", "$R, $V$lane",
5812 imm:$lane))]> {
5813 let Inst{21} = lane{1};
5814 let Inst{6} = lane{0};
5817 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
5818 IIC_VMOVSI, "vmov", "u8", "$R, $V$lane",
5820 imm:$lane))]> {
5821 let Inst{21} = lane{2};
5822 let Inst{6-5} = lane{1-0};
5825 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
5826 IIC_VMOVSI, "vmov", "u16", "$R, $V$lane",
5828 imm:$lane))]> {
5829 let Inst{21} = lane{1};
5830 let Inst{6} = lane{0};
5833 (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane),
5834 IIC_VMOVSI, "vmov", "32", "$R, $V$lane",
5836 imm:$lane))]>,
5838 let Inst{21} = lane{0};
5841 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
5843 (DSubReg_i8_reg imm:$lane))),
5844 (SubReg_i8_lane imm:$lane))>;
5845 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
5847 (DSubReg_i16_reg imm:$lane))),
5848 (SubReg_i16_lane imm:$lane))>;
5849 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
5851 (DSubReg_i8_reg imm:$lane))),
5852 (SubReg_i8_lane imm:$lane))>;
5853 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
5855 (DSubReg_i16_reg imm:$lane))),
5856 (SubReg_i16_lane imm:$lane))>;
5857 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
5859 (DSubReg_i32_reg imm:$lane))),
5860 (SubReg_i32_lane imm:$lane))>,
5862 def : Pat<(extractelt (v2i32 DPR:$src), imm:$lane),
5864 (i32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
5866 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
5868 (i32 (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
5886 (ins DPR:$src1, GPR:$R, VectorIndex8:$lane),
5887 IIC_VMOVISL, "vmov", "8", "$V$lane, $R",
5889 GPR:$R, imm:$lane))]> {
5890 let Inst{21} = lane{2};
5891 let Inst{6-5} = lane{1-0};
5894 (ins DPR:$src1, GPR:$R, VectorIndex16:$lane),
5895 IIC_VMOVISL, "vmov", "16", "$V$lane, $R",
5897 GPR:$R, imm:$lane))]> {
5898 let Inst{21} = lane{1};
5899 let Inst{6} = lane{0};
5902 (ins DPR:$src1, GPR:$R, VectorIndex32:$lane),
5903 IIC_VMOVISL, "vmov", "32", "$V$lane, $R",
5905 GPR:$R, imm:$lane))]>,
5907 let Inst{21} = lane{0};
5913 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
5916 (DSubReg_i8_reg imm:$lane))),
5917 GPR:$src2, (SubReg_i8_lane imm:$lane))),
5918 (DSubReg_i8_reg imm:$lane)))>;
5919 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
5922 (DSubReg_i16_reg imm:$lane))),
5923 GPR:$src2, (SubReg_i16_lane imm:$lane))),
5924 (DSubReg_i16_reg imm:$lane)))>;
5925 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
5928 (DSubReg_i32_reg imm:$lane))),
5929 GPR:$src2, (SubReg_i32_lane imm:$lane))),
5930 (DSubReg_i32_reg imm:$lane)))>;
6005 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
6006 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
6007 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
6011 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
6012 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
6014 VectorIndex32:$lane)))]>;
6019 bits<3> lane;
6020 let Inst{19-17} = lane{2-0};
6023 bits<2> lane;
6024 let Inst{19-18} = lane{1-0};
6027 bits<1> lane;
6028 let Inst{19} = lane{0};
6031 bits<3> lane;
6032 let Inst{19-17} = lane{2-0};
6035 bits<2> lane;
6036 let Inst{19-18} = lane{1-0};
6039 bits<1> lane;
6040 let Inst{19} = lane{0};
6043 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
6044 (VDUPLN32d DPR:$Vm, imm:$lane)>;
6046 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
6047 (VDUPLN32q DPR:$Vm, imm:$lane)>;
6049 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
6051 (DSubReg_i8_reg imm:$lane))),
6052 (SubReg_i8_lane imm:$lane)))>;
6053 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
6055 (DSubReg_i16_reg imm:$lane))),
6056 (SubReg_i16_lane imm:$lane)))>;
6057 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
6059 (DSubReg_i32_reg imm:$lane))),
6060 (SubReg_i32_lane imm:$lane)))>;
6061 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
6063 (DSubReg_i32_reg imm:$lane))),
6064 (SubReg_i32_lane imm:$lane)))>;
6689 def : VFPPat<(f64 (sint_to_fp (extractelt (v2i32 DPR:$src), imm:$lane))),
6690 (VSITOD (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6691 def : VFPPat<(f64 (sint_to_fp (extractelt (v4i32 QPR:$src), imm:$lane))),
6692 (VSITOD (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6693 def : VFPPat<(f64 (uint_to_fp (extractelt (v2i32 DPR:$src), imm:$lane))),
6694 (VUITOD (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6695 def : VFPPat<(f64 (uint_to_fp (extractelt (v4i32 QPR:$src), imm:$lane))),
6696 (VUITOD (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6850 def : Pat<(f32 (bitconvert (i32 (extractelt (v2i32 DPR:$src), imm:$lane)))),
6851 (f32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
7179 // VLD1 single-lane pseudo-instructions. These need special handling for
7180 // the lane index that an InstAlias can't handle, so we use these instead.
7217 // VST1 single-lane pseudo-instructions. These need special handling for
7218 // the lane index that an InstAlias can't handle, so we use these instead.
7254 // VLD2 single-lane pseudo-instructions. These need special handling for
7255 // the lane index that an InstAlias can't handle, so we use these instead.
7313 // VST2 single-lane pseudo-instructions. These need special handling for
7314 // the lane index that an InstAlias can't handle, so we use these instead.
7373 // the lane index that an InstAlias can't handle, so we use these instead.
7443 // VLD3 single-lane pseudo-instructions. These need special handling for
7444 // the lane index that an InstAlias can't handle, so we use these instead.
7561 // VST3 single-lane pseudo-instructions. These need special handling for
7562 // the lane index that an InstAlias can't handle, so we use these instead.
7681 // the lane index that an InstAlias can't handle, so we use these instead.
7751 // VLD4 single-lane pseudo-instructions. These need special handling for
7752 // the lane index that an InstAlias can't handle, so we use these instead.
7883 // VST4 single-lane pseudo-instructions. These need special handling for
7884 // the lane index that an InstAlias can't handle, so we use these instead.