Lines Matching refs:Operands
192 bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
194 bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
246 OperandVector &Operands);
337 bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
338 bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
372 SMLoc NameLoc, OperandVector &Operands) override;
380 OperandVector &Operands, MCStreamer &Out,
2971 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) { in tryParseShiftRegister() argument
2997 (ARMOperand *)Operands.pop_back_val().release()); in tryParseShiftRegister()
3057 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, in tryParseShiftRegister()
3061 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, in tryParseShiftRegister()
3074 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) { in tryParseRegisterWithWriteBack() argument
3081 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(), in tryParseRegisterWithWriteBack()
3086 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), in tryParseRegisterWithWriteBack()
3112 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), in tryParseRegisterWithWriteBack()
3171 ARMAsmParser::parseITCondCode(OperandVector &Operands) { in parseITCondCode() argument
3200 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); in parseITCondCode()
3209 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) { in parseCoprocNumOperand() argument
3224 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); in parseCoprocNumOperand()
3232 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) { in parseCoprocRegOperand() argument
3244 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); in parseCoprocRegOperand()
3251 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) { in parseCoprocOptionOperand() argument
3279 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); in parseCoprocOptionOperand()
3329 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) { in parseRegisterList() argument
3448 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); in parseRegisterList()
3452 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); in parseRegisterList()
3513 ARMAsmParser::parseVectorList(OperandVector &Operands) { in parseVectorList() argument
3532 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); in parseVectorList()
3535 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, in parseVectorList()
3539 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, in parseVectorList()
3555 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); in parseVectorList()
3560 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, in parseVectorList()
3564 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, in parseVectorList()
3737 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, in parseVectorList()
3749 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, in parseVectorList()
3754 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, in parseVectorList()
3765 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) { in parseMemBarrierOptOperand() argument
3831 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); in parseMemBarrierOptOperand()
3837 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) { in parseInstSyncBarrierOptOperand() argument
3881 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt( in parseInstSyncBarrierOptOperand()
3889 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) { in parseProcIFlagsOperand() argument
3918 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); in parseProcIFlagsOperand()
3924 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) { in parseMSRMaskOperand() argument
3987 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); in parseMSRMaskOperand()
4050 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); in parseMSRMaskOperand()
4057 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) { in parseBankedRegOperand() argument
4107 Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S)); in parseBankedRegOperand()
4112 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low, in parsePKHImm() argument
4155 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc)); in parsePKHImm()
4161 ARMAsmParser::parseSetEndImm(OperandVector &Operands) { in parseSetEndImm() argument
4179 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val, in parseSetEndImm()
4191 ARMAsmParser::parseShifterImm(OperandVector &Operands) { in parseShifterImm() argument
4253 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc)); in parseShifterImm()
4262 ARMAsmParser::parseRotImm(OperandVector &Operands) { in parseRotImm() argument
4303 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc)); in parseRotImm()
4309 ARMAsmParser::parseModImm(OperandVector &Operands) { in parseModImm() argument
4356 Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF), in parseModImm()
4369 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1)); in parseModImm()
4375 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1)); in parseModImm()
4414 Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2)); in parseModImm()
4426 ARMAsmParser::parseBitfield(OperandVector &Operands) { in parseBitfield() argument
4489 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc)); in parseBitfield()
4495 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) { in parsePostIdxReg() argument
4538 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, in parsePostIdxReg()
4545 ARMAsmParser::parseAM3Offset(OperandVector &Operands) { in parseAM3Offset() argument
4582 Operands.push_back( in parseAM3Offset()
4609 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, in parseAM3Offset()
4619 const OperandVector &Operands) { in cvtThumbMultiply() argument
4620 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); in cvtThumbMultiply()
4621 ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1); in cvtThumbMultiply()
4625 if (Operands.size() == 6 && in cvtThumbMultiply()
4626 ((ARMOperand &)*Operands[4]).getReg() == in cvtThumbMultiply()
4627 ((ARMOperand &)*Operands[3]).getReg()) in cvtThumbMultiply()
4629 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1); in cvtThumbMultiply()
4631 ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2); in cvtThumbMultiply()
4635 const OperandVector &Operands) { in cvtThumbBranches() argument
4658 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode(); in cvtThumbBranches()
4675 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); in cvtThumbBranches()
4682 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]); in cvtThumbBranches()
4688 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1); in cvtThumbBranches()
4689 ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2); in cvtThumbBranches()
4694 bool ARMAsmParser::parseMemory(OperandVector &Operands) { in parseMemory() argument
4717 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0, in parseMemory()
4724 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); in parseMemory()
4774 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0, in parseMemory()
4781 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); in parseMemory()
4823 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, in parseMemory()
4830 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); in parseMemory()
4867 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum, in parseMemory()
4874 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); in parseMemory()
4947 ARMAsmParser::parseFPImm(OperandVector &Operands) { in parseFPImm() argument
4974 ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]); in parseFPImm()
4977 ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]); in parseFPImm()
4999 Operands.push_back(ARMOperand::CreateImm( in parseFPImm()
5016 Operands.push_back(ARMOperand::CreateImm( in parseFPImm()
5028 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { in parseOperand() argument
5034 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); in parseOperand()
5053 if (!tryParseRegisterWithWriteBack(Operands)) in parseOperand()
5055 int Res = tryParseShiftRegister(Operands); in parseOperand()
5065 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S)); in parseOperand()
5084 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); in parseOperand()
5088 return parseMemory(Operands); in parseOperand()
5090 return parseRegisterList(Operands); in parseOperand()
5109 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); in parseOperand()
5115 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(), in parseOperand()
5140 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); in parseOperand()
5156 Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E)); in parseOperand()
5400 OperandVector &Operands) { in tryConvertingToTwoOperandForm() argument
5401 if (Operands.size() != 6) in tryConvertingToTwoOperandForm()
5404 const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]); in tryConvertingToTwoOperandForm()
5405 auto &Op4 = static_cast<ARMOperand &>(*Operands[4]); in tryConvertingToTwoOperandForm()
5416 auto &Op5 = static_cast<ARMOperand &>(*Operands[5]); in tryConvertingToTwoOperandForm()
5476 Operands.erase(Operands.begin() + 3); in tryConvertingToTwoOperandForm()
5481 OperandVector &Operands) { in shouldOmitCCOutOperand() argument
5493 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && in shouldOmitCCOutOperand()
5494 !static_cast<ARMOperand &>(*Operands[4]).isModImm() && in shouldOmitCCOutOperand()
5495 static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() && in shouldOmitCCOutOperand()
5496 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0) in shouldOmitCCOutOperand()
5501 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && in shouldOmitCCOutOperand()
5502 static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
5503 static_cast<ARMOperand &>(*Operands[4]).isReg() && in shouldOmitCCOutOperand()
5504 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0) in shouldOmitCCOutOperand()
5512 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
5513 static_cast<ARMOperand &>(*Operands[4]).isReg() && in shouldOmitCCOutOperand()
5514 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP && in shouldOmitCCOutOperand()
5515 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && in shouldOmitCCOutOperand()
5516 ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) || in shouldOmitCCOutOperand()
5517 static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4())) in shouldOmitCCOutOperand()
5525 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
5526 static_cast<ARMOperand &>(*Operands[4]).isReg() && in shouldOmitCCOutOperand()
5527 static_cast<ARMOperand &>(*Operands[5]).isImm()) { in shouldOmitCCOutOperand()
5533 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) && in shouldOmitCCOutOperand()
5534 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) && in shouldOmitCCOutOperand()
5535 static_cast<ARMOperand &>(*Operands[5]).isImm0_7()) in shouldOmitCCOutOperand()
5539 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC && in shouldOmitCCOutOperand()
5540 static_cast<ARMOperand &>(*Operands[5]).isT2SOImm()) in shouldOmitCCOutOperand()
5551 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && in shouldOmitCCOutOperand()
5552 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && in shouldOmitCCOutOperand()
5553 static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
5554 static_cast<ARMOperand &>(*Operands[4]).isReg() && in shouldOmitCCOutOperand()
5555 static_cast<ARMOperand &>(*Operands[5]).isReg() && in shouldOmitCCOutOperand()
5560 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || in shouldOmitCCOutOperand()
5561 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || in shouldOmitCCOutOperand()
5562 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) || in shouldOmitCCOutOperand()
5563 !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() != in shouldOmitCCOutOperand()
5564 static_cast<ARMOperand &>(*Operands[5]).getReg() && in shouldOmitCCOutOperand()
5565 static_cast<ARMOperand &>(*Operands[3]).getReg() != in shouldOmitCCOutOperand()
5566 static_cast<ARMOperand &>(*Operands[4]).getReg()))) in shouldOmitCCOutOperand()
5571 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && in shouldOmitCCOutOperand()
5572 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && in shouldOmitCCOutOperand()
5573 static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
5574 static_cast<ARMOperand &>(*Operands[4]).isReg() && in shouldOmitCCOutOperand()
5578 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) || in shouldOmitCCOutOperand()
5579 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) || in shouldOmitCCOutOperand()
5591 (Operands.size() == 5 || Operands.size() == 6) && in shouldOmitCCOutOperand()
5592 static_cast<ARMOperand &>(*Operands[3]).isReg() && in shouldOmitCCOutOperand()
5593 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP && in shouldOmitCCOutOperand()
5594 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 && in shouldOmitCCOutOperand()
5595 (static_cast<ARMOperand &>(*Operands[4]).isImm() || in shouldOmitCCOutOperand()
5596 (Operands.size() == 6 && in shouldOmitCCOutOperand()
5597 static_cast<ARMOperand &>(*Operands[5]).isImm()))) in shouldOmitCCOutOperand()
5604 OperandVector &Operands) { in shouldOmitPredicateOperand() argument
5608 (static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32" || in shouldOmitPredicateOperand()
5609 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f16")) { in shouldOmitPredicateOperand()
5610 if (static_cast<ARMOperand &>(*Operands[3]).isToken() && in shouldOmitPredicateOperand()
5611 (static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32" || in shouldOmitPredicateOperand()
5612 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f16")) in shouldOmitPredicateOperand()
5615 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() && in shouldOmitPredicateOperand()
5617 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) || in shouldOmitPredicateOperand()
5619 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()))) in shouldOmitPredicateOperand()
5664 SMLoc NameLoc, OperandVector &Operands) { in ParseInstruction() argument
5710 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); in ParseInstruction()
5734 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); in ParseInstruction()
5768 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, in ParseInstruction()
5776 Operands.push_back(ARMOperand::CreateCondCode( in ParseInstruction()
5782 Operands.push_back(ARMOperand::CreateImm( in ParseInstruction()
5814 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); in ParseInstruction()
5821 if (parseOperand(Operands, Mnemonic)) { in ParseInstruction()
5830 if (parseOperand(Operands, Mnemonic)) { in ParseInstruction()
5846 ARMOperand &Op = static_cast<ARMOperand &>(*Operands.back()); in ParseInstruction()
5855 tryConvertingToTwoOperandForm(Mnemonic, CarrySetting, Operands); in ParseInstruction()
5864 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) in ParseInstruction()
5865 Operands.erase(Operands.begin() + 1); in ParseInstruction()
5870 if (shouldOmitPredicateOperand(Mnemonic, Operands)) in ParseInstruction()
5871 Operands.erase(Operands.begin() + 1); in ParseInstruction()
5878 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && in ParseInstruction()
5879 static_cast<ARMOperand &>(*Operands[2]).isImm()) in ParseInstruction()
5880 Operands.erase(Operands.begin() + 1); in ParseInstruction()
5888 if (!isThumb() && Operands.size() > 4 && in ParseInstruction()
5893 ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]); in ParseInstruction()
5894 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]); in ParseInstruction()
5914 Operands[Idx] = in ParseInstruction()
5916 Operands.erase(Operands.begin() + Idx + 1); in ParseInstruction()
5922 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]); in ParseInstruction()
5923 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]); in ParseInstruction()
5934 Operands.insert( in ParseInstruction()
5935 Operands.begin() + 3, in ParseInstruction()
5945 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 && in ParseInstruction()
5946 static_cast<ARMOperand &>(*Operands[3]).isReg() && in ParseInstruction()
5947 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC && in ParseInstruction()
5948 static_cast<ARMOperand &>(*Operands[4]).isReg() && in ParseInstruction()
5949 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR && in ParseInstruction()
5950 static_cast<ARMOperand &>(*Operands[5]).isImm()) { in ParseInstruction()
5951 Operands.front() = ARMOperand::CreateToken(Name, NameLoc); in ParseInstruction()
5952 Operands.erase(Operands.begin() + 1); in ParseInstruction()
5999 const OperandVector &Operands, in validatetLDMRegList() argument
6001 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]); in validatetLDMRegList()
6009 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetLDMRegList()
6012 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetLDMRegList()
6015 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetLDMRegList()
6022 const OperandVector &Operands, in validatetSTMRegList() argument
6024 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]); in validatetSTMRegList()
6031 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetSTMRegList()
6034 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetSTMRegList()
6037 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(), in validatetSTMRegList()
6044 const OperandVector &Operands) { in validateInstruction() argument
6046 SMLoc Loc = Operands[0]->getStartLoc(); in validateInstruction()
6066 for (unsigned I = 1; I < Operands.size(); ++I) in validateInstruction()
6067 if (static_cast<ARMOperand &>(*Operands[I]).isCondCode()) in validateInstruction()
6068 CondLoc = Operands[I]->getStartLoc(); in validateInstruction()
6090 return Error(Operands[3]->getStartLoc(), in validateInstruction()
6096 return Error(Operands[3]->getStartLoc(), in validateInstruction()
6102 return Error(Operands[3]->getStartLoc(), in validateInstruction()
6110 return Error(Operands[3]->getStartLoc(), in validateInstruction()
6124 return Error(Operands[3]->getStartLoc(), in validateInstruction()
6132 return Error(Operands[2]->getStartLoc(), in validateInstruction()
6141 return Error(Operands[3]->getStartLoc(), in validateInstruction()
6151 return Error(Operands[3]->getStartLoc(), in validateInstruction()
6170 return Error(Operands[3]->getStartLoc(), in validateInstruction()
6193 return Error(Operands[3]->getStartLoc(), in validateInstruction()
6203 return Error(Operands[5]->getStartLoc(), in validateInstruction()
6217 (static_cast<ARMOperand &>(*Operands[3]).isToken() && in validateInstruction()
6218 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!"); in validateInstruction()
6221 return Error(Operands[3 + HasWritebackToken]->getStartLoc(), in validateInstruction()
6225 return Error(Operands[2]->getStartLoc(), in validateInstruction()
6230 return Error(Operands[3]->getStartLoc(), in validateInstruction()
6234 if (validatetLDMRegList(Inst, Operands, 3)) in validateInstruction()
6247 return Error(Operands.back()->getStartLoc(), in validateInstruction()
6252 if (validatetLDMRegList(Inst, Operands, 3)) in validateInstruction()
6257 if (validatetSTMRegList(Inst, Operands, 3)) in validateInstruction()
6265 return Error(Operands.back()->getStartLoc(), in validateInstruction()
6269 if (validatetLDMRegList(Inst, Operands, 3)) in validateInstruction()
6272 if (validatetSTMRegList(Inst, Operands, 3)) in validateInstruction()
6282 return Error(Operands[4]->getStartLoc(), in validateInstruction()
6290 return Error(Operands[2]->getStartLoc(), in validateInstruction()
6301 if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() != in validateInstruction()
6302 ((ARMOperand &)*Operands[5]).getReg()) && in validateInstruction()
6303 (((ARMOperand &)*Operands[3]).getReg() != in validateInstruction()
6304 ((ARMOperand &)*Operands[4]).getReg())) { in validateInstruction()
6305 return Error(Operands[3]->getStartLoc(), in validateInstruction()
6317 return Error(Operands[2]->getStartLoc(), in validateInstruction()
6319 if (validatetLDMRegList(Inst, Operands, 2, !isMClass())) in validateInstruction()
6327 return Error(Operands[2]->getStartLoc(), in validateInstruction()
6329 if (validatetSTMRegList(Inst, Operands, 2)) in validateInstruction()
6338 return Error(Operands[4]->getStartLoc(), in validateInstruction()
6344 return Error(Operands[4]->getStartLoc(), in validateInstruction()
6348 if (validatetSTMRegList(Inst, Operands, 4)) in validateInstruction()
6357 return Error(Operands[4]->getStartLoc(), in validateInstruction()
6364 if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>()) in validateInstruction()
6365 return Error(Operands[2]->getStartLoc(), "branch target out of range"); in validateInstruction()
6368 int op = (Operands[2]->isImm()) ? 2 : 3; in validateInstruction()
6369 if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>()) in validateInstruction()
6370 return Error(Operands[op]->getStartLoc(), "branch target out of range"); in validateInstruction()
6375 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>()) in validateInstruction()
6376 return Error(Operands[2]->getStartLoc(), "branch target out of range"); in validateInstruction()
6379 int Op = (Operands[2]->isImm()) ? 2 : 3; in validateInstruction()
6380 if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>()) in validateInstruction()
6381 return Error(Operands[Op]->getStartLoc(), "branch target out of range"); in validateInstruction()
6394 int i = (Operands[3]->isImm()) ? 3 : 4; in validateInstruction()
6395 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]); in validateInstruction()
6670 const OperandVector &Operands, in processInstruction() argument
6751 !(static_cast<ARMOperand &>(*Operands[2]).isToken() && in processInstruction()
6752 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".w")) in processInstruction()
7842 !(static_cast<ARMOperand &>(*Operands[3]).isToken() && in processInstruction()
7843 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) { in processInstruction()
8046 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" && in processInstruction()
8064 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" && in processInstruction()
8080 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" || in processInstruction()
8089 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" || in processInstruction()
8100 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { in processInstruction()
8110 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { in processInstruction()
8126 (static_cast<ARMOperand &>(*Operands[3]).isToken() && in processInstruction()
8127 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) in processInstruction()
8156 (static_cast<ARMOperand &>(*Operands[3]).isToken() && in processInstruction()
8157 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) in processInstruction()
8214 (static_cast<ARMOperand &>(*Operands[3]).isToken() && in processInstruction()
8215 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!"); in processInstruction()
8279 (!static_cast<ARMOperand &>(*Operands[2]).isToken() || in processInstruction()
8280 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) { in processInstruction()
8301 (!static_cast<ARMOperand &>(*Operands[2]).isToken() || in processInstruction()
8302 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) { in processInstruction()
8324 (!static_cast<ARMOperand &>(*Operands[2]).isToken() || in processInstruction()
8325 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) { in processInstruction()
8438 (!static_cast<ARMOperand &>(*Operands[3]).isToken() || in processInstruction()
8439 !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower( in processInstruction()
8478 (!static_cast<ARMOperand &>(*Operands[3]).isToken() || in processInstruction()
8479 !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower( in processInstruction()
8572 OperandVector &Operands, in MatchAndEmitInstruction() argument
8578 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, in MatchAndEmitInstruction()
8584 if (validateInstruction(Inst, Operands)) { in MatchAndEmitInstruction()
8598 while (processInstruction(Inst, Operands, Out)) in MatchAndEmitInstruction()
8639 if (ErrorInfo >= Operands.size()) in MatchAndEmitInstruction()
8642 ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc(); in MatchAndEmitInstruction()
8650 ((ARMOperand &)*Operands[0]).getLocRange()); in MatchAndEmitInstruction()
8662 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc(); in MatchAndEmitInstruction()
8667 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc(); in MatchAndEmitInstruction()
8683 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getAlignmentLoc(); in MatchAndEmitInstruction()
9463 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands; in parseDirectiveRegSave() local
9466 if (parseRegisterList(Operands)) in parseDirectiveRegSave()
9468 ARMOperand &Op = (ARMOperand &)*Operands[0]; in parseDirectiveRegSave()