208   for (auto &VA : ArgLocs) {  in LowerFormalArguments()  local
209     if (VA.isRegLoc()) {  in LowerFormalArguments()
211       EVT RegVT = VA.getLocVT();  in LowerFormalArguments()
220         RegInfo.addLiveIn(VA.getLocReg(), VReg);  in LowerFormalArguments()
226         if (VA.getLocInfo() == CCValAssign::SExt)  in LowerFormalArguments()
228                                  DAG.getValueType(VA.getValVT()));  in LowerFormalArguments()
229         else if (VA.getLocInfo() == CCValAssign::ZExt)  in LowerFormalArguments()
231                                  DAG.getValueType(VA.getValVT()));  in LowerFormalArguments()
233         if (VA.getLocInfo() != CCValAssign::Full)  in LowerFormalArguments()
234           ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);  in LowerFormalArguments()
311     CCValAssign &VA = ArgLocs[i];  in LowerCall()  local
315     switch (VA.getLocInfo()) {  in LowerCall()
321       Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg);  in LowerCall()
324       Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg);  in LowerCall()
327       Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg);  in LowerCall()
332     if (VA.isRegLoc())  in LowerCall()
333       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));  in LowerCall()
414     CCValAssign &VA = RVLocs[i];  in LowerReturn()  local
415     assert(VA.isRegLoc() && "Can only return in registers!");  in LowerReturn()
417     Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);  in LowerReturn()
422     RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));  in LowerReturn()