Lines Matching defs:const
234 int &FrameIndex) const { in isLoadFromStackSlot()
259 int &FrameIndex) const { in isStoreToStackSlot()
297 bool AllowModify) const { in AnalyzeBranch()
459 unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { in RemoveBranch()
482 ArrayRef<MachineOperand> Cond, DebugLoc DL) const { in InsertBranch()
577 BranchProbability Probability) const { in isProfitableToIfCvt()
584 unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability) in isProfitableToIfCvt()
591 unsigned NumInstrs, BranchProbability Probability) const { in isProfitableToDupForIfCvt()
598 unsigned SrcReg, bool KillSrc) const { in copyPhysReg()
706 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { in storeRegToStackSlot() argument
736 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { in loadRegFromStackSlot() argument
766 bool HexagonInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) in expandPostRAPseudo()
1008 SmallVectorImpl<MachineOperand> &Cond) const { in ReverseBranchCondition()
1024 MachineBasicBlock::iterator MI) const { in insertNoop()
1038 bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const { in isPredicated() argument
1045 ArrayRef<MachineOperand> Cond) const { in PredicateInstruction()
1097 ArrayRef<MachineOperand> Pred2) const { in SubsumesPredicate()
1104 std::vector<MachineOperand> &Pred) const { in DefinesPredicate()
1119 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const { in isPredicable()
1208 const MachineBasicBlock *MBB, const MachineFunction &MF) const { in isSchedulingBoundary() argument
1253 const MCAsmInfo &MAI) const { in getInlineAsmLength() argument
1280 const InstrItineraryData *II, const ScheduleDAG *DAG) const { in CreateTargetPostRAHazardRecognizer() argument
1290 unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const { in analyzeCompare()
1375 const MachineInstr *MI, unsigned *PredCost) const { in getInstrLatency()
1381 const TargetSubtargetInfo &STI) const { in CreateTargetScheduleState() argument
1392 MachineInstr *MIb, AliasAnalysis *AA) const { in areMemAccessesTriviallyDisjoint()
1432 unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const { in createVR()
1450 bool HexagonInstrInfo::isAbsoluteSet(const MachineInstr* MI) const { in isAbsoluteSet() argument
1455 bool HexagonInstrInfo::isAccumulator(const MachineInstr *MI) const { in isAccumulator() argument
1461 bool HexagonInstrInfo::isComplex(const MachineInstr *MI) const { in isComplex() argument
1483 bool HexagonInstrInfo::isCompoundBranchInstr(const MachineInstr *MI) const { in isCompoundBranchInstr() argument
1488 bool HexagonInstrInfo::isCondInst(const MachineInstr *MI) const { in isCondInst() argument
1499 bool HexagonInstrInfo::isConditionalALU32(const MachineInstr* MI) const { in isConditionalALU32() argument
1559 bool HexagonInstrInfo::isConditionalLoad(const MachineInstr* MI) const { in isConditionalLoad() argument
1573 bool HexagonInstrInfo::isConditionalStore(const MachineInstr* MI) const { in isConditionalStore() argument
1627 bool HexagonInstrInfo::isConditionalTransfer(const MachineInstr *MI) const { in isConditionalTransfer() argument
1650 bool HexagonInstrInfo::isConstExtended(const MachineInstr *MI) const { in isConstExtended() argument
1697 bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const { in isDeallocRet() argument
1714 const MachineInstr *ConsMI) const { in isDependent() argument
1751 bool HexagonInstrInfo::isDotCurInst(const MachineInstr* MI) const { in isDotCurInst() argument
1765 bool HexagonInstrInfo::isDotNewInst(const MachineInstr* MI) const { in isDotNewInst() argument
1776 const MachineInstr *MIb) const { in isDuplexPair() argument
1783 bool HexagonInstrInfo::isEarlySourceInstr(const MachineInstr *MI) const { in isEarlySourceInstr() argument
1798 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const { in isEndLoopN()
1804 bool HexagonInstrInfo::isExpr(unsigned OpType) const { in isExpr()
1819 bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const { in isExtendable() argument
1841 bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const { in isExtended() argument
1857 bool HexagonInstrInfo::isFloat(const MachineInstr *MI) const { in isFloat() argument
1866 const MachineInstr *J) const { in isHVXMemWithAIndirect() argument
1875 bool HexagonInstrInfo::isIndirectCall(const MachineInstr *MI) const { in isIndirectCall() argument
1886 bool HexagonInstrInfo::isIndirectL4Return(const MachineInstr *MI) const { in isIndirectL4Return() argument
1901 bool HexagonInstrInfo::isJumpR(const MachineInstr *MI) const { in isJumpR() argument
1921 unsigned offset) const { in isJumpWithinBranchRange()
1962 const MachineInstr *ESMI) const { in isLateInstrFeedsEarlyInstr() argument
1983 bool HexagonInstrInfo::isLateResultInstr(const MachineInstr *MI) const { in isLateResultInstr() argument
2023 bool HexagonInstrInfo::isLateSourceInstr(const MachineInstr *MI) const { in isLateSourceInstr() argument
2033 bool HexagonInstrInfo::isLoopN(const MachineInstr *MI) const { in isLoopN() argument
2046 bool HexagonInstrInfo::isMemOp(const MachineInstr *MI) const { in isMemOp() argument
2079 bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const { in isNewValue() argument
2085 bool HexagonInstrInfo::isNewValue(unsigned Opcode) const { in isNewValue()
2091 bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const { in isNewValueInst() argument
2096 bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const { in isNewValueJump() argument
2101 bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const { in isNewValueJump()
2106 bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const { in isNewValueStore() argument
2112 bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const { in isNewValueStore()
2120 unsigned OperandNum) const { in isOperandExtended()
2127 bool HexagonInstrInfo::isPostIncrement(const MachineInstr* MI) const { in isPostIncrement() argument
2132 bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const { in isPredicatedNew() argument
2139 bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const { in isPredicatedNew()
2146 bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr *MI) const { in isPredicatedTrue() argument
2153 bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const { in isPredicatedTrue()
2162 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const { in isPredicated()
2168 bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const { in isPredicateLate()
2174 bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const { in isPredictedTaken()
2182 bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const { in isSaveCalleeSavedRegsCall() argument
2188 bool HexagonInstrInfo::isSolo(const MachineInstr* MI) const { in isSolo() argument
2194 bool HexagonInstrInfo::isSpillPredRegOp(const MachineInstr *MI) const { in isSpillPredRegOp() argument
2206 bool HexagonInstrInfo::isTC1(const MachineInstr *MI) const { in isTC1() argument
2225 bool HexagonInstrInfo::isTC2(const MachineInstr *MI) const { in isTC2() argument
2242 bool HexagonInstrInfo::isTC2Early(const MachineInstr *MI) const { in isTC2Early() argument
2263 bool HexagonInstrInfo::isTC4x(const MachineInstr *MI) const { in isTC4x() argument
2272 bool HexagonInstrInfo::isV60VectorInstruction(const MachineInstr *MI) const { in isV60VectorInstruction() argument
2283 bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, const int Offset) const { in isValidAutoIncImm() argument
2321 bool Extend) const { in isValidOffset()
2479 bool HexagonInstrInfo::isVecAcc(const MachineInstr *MI) const { in isVecAcc() argument
2484 bool HexagonInstrInfo::isVecALU(const MachineInstr *MI) const { in isVecALU() argument
2496 const MachineInstr *ConsMI) const { in isVecUsableNextPacket() argument
2512 const MachineInstr *Second) const { in canExecuteInBundle() argument
2532 bool HexagonInstrInfo::hasEHLabel(const MachineBasicBlock *B) const { in hasEHLabel() argument
2542 bool HexagonInstrInfo::hasNonExtEquivalent(const MachineInstr *MI) const { in hasNonExtEquivalent() argument
2578 bool HexagonInstrInfo::hasPseudoInstrPair(const MachineInstr *MI) const { in hasPseudoInstrPair() argument
2584 bool HexagonInstrInfo::hasUncondBranch(const MachineBasicBlock *B) in hasUncondBranch()
2597 bool HexagonInstrInfo::mayBeCurLoad(const MachineInstr *MI) const { in mayBeCurLoad() argument
2606 bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const { in mayBeNewStore() argument
2613 const MachineInstr *ConsMI) const { in producesStall() argument
2632 MachineBasicBlock::const_instr_iterator BII) const { in producesStall()
2659 unsigned PredReg) const { in predCanBeUsedAsDotNew()
2673 bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const { in PredOpcodeHasJMP_c()
2683 bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const { in predOpcodeHasNot()
2690 unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const { in getAddrMode() argument
2699 int &Offset, unsigned &AccessSize) const { in getBaseAndOffset()
2735 unsigned &BasePos, unsigned &OffsetPos) const { in getBaseAndOffsetPosition()
2772 MachineBasicBlock& MBB) const { in getBranchingInstrs()
2830 unsigned HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const { in getCExtOpNum() argument
2838 const MachineInstr *MI) const { in getCompoundCandidateGroup() argument
2927 const MachineInstr *GB) const { in getCompoundOpcode() argument
2944 int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const { in getCondOpcode()
2965 int HexagonInstrInfo::getDotCurOp(const MachineInstr* MI) const { in getDotCurOp() argument
3064 int HexagonInstrInfo::getDotNewOp(const MachineInstr* MI) const { in getDotNewOp() argument
3109 const MachineBranchProbabilityInfo *MBPI) const { in getDotNewPredJumpOp() argument
3134 const MachineBranchProbabilityInfo *MBPI) const { in getDotNewPredOp() argument
3152 int HexagonInstrInfo::getDotOldOp(const int opc) const { in getDotOldOp() argument
3171 const MachineInstr *MI) const { in getDuplexCandidateGroup() argument
3512 short HexagonInstrInfo::getEquivalentHWInstr(const MachineInstr *MI) const { in getEquivalentHWInstr() argument
3518 MachineInstr *HexagonInstrInfo::getFirstNonDbgInst(MachineBasicBlock *BB) in getFirstNonDbgInst()
3531 const InstrItineraryData *ItinData, const MachineInstr *MI) const { in getInstrTimingClassLatency() argument
3556 SmallVectorImpl<MachineOperand> &Cond) const { in getInvertedPredSense()
3565 unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const { in getInvertedPredicatedOpcode() argument
3577 int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const { in getMaxValue() argument
3591 unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr* MI) const { in getMemAccessSize() argument
3598 int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const { in getMinValue() argument
3613 short HexagonInstrInfo::getNonExtOpcode(const MachineInstr *MI) const { in getNonExtOpcode() argument
3639 unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const { in getPredReg()
3659 short HexagonInstrInfo::getPseudoInstrPair(const MachineInstr *MI) const { in getPseudoInstrPair() argument
3664 short HexagonInstrInfo::getRegForm(const MachineInstr *MI) const { in getRegForm() argument
3673 unsigned HexagonInstrInfo::getSize(const MachineInstr *MI) const { in getSize() argument
3708 uint64_t HexagonInstrInfo::getType(const MachineInstr* MI) const { in getType() argument
3714 unsigned HexagonInstrInfo::getUnits(const MachineInstr* MI) const { in getUnits() argument
3723 unsigned HexagonInstrInfo::getValidSubTargets(const unsigned Opcode) const { in getValidSubTargets() argument
3730 unsigned HexagonInstrInfo::nonDbgBBSize(const MachineBasicBlock *BB) const { in nonDbgBBSize() argument
3736 MachineBasicBlock::const_iterator BundleHead) const { in nonDbgBundleSize()
3746 void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const { in immediateExtend()
3761 MachineInstr* MI, MachineBasicBlock* NewTarget) const { in invertAndChangeJumpTarget()
3781 void HexagonInstrInfo::genAllInsnTimingClasses(MachineFunction &MF) const { in genAllInsnTimingClasses()
3804 bool HexagonInstrInfo::reversePredSense(MachineInstr* MI) const { in reversePredSense()
3812 unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const { in reversePrediction()
3824 bool HexagonInstrInfo::validateBranchCond(const ArrayRef<MachineOperand> &Cond) in validateBranchCond()