Lines Matching refs:VA
2641 CCValAssign &VA = ArgLocs[i]; in LowerCall() local
2642 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); in LowerCall()
2659 VA); in LowerCall()
2665 switch (VA.getLocInfo()) { in LowerCall()
2669 if (VA.isRegLoc()) { in LowerCall()
2681 unsigned LocRegLo = VA.getLocReg(); in LowerCall()
2714 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); in LowerCall()
2716 ISD::SHL, DL, VA.getLocVT(), Arg, in LowerCall()
2717 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); in LowerCall()
2722 if (VA.isRegLoc()) { in LowerCall()
2723 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
2728 assert(VA.isMemLoc()); in LowerCall()
2732 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(), in LowerCall()
2831 CCValAssign &VA = RVLocs[i]; in LowerCallResult() local
2832 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerCallResult()
2839 if (VA.isUpperBitsInLoc()) { in LowerCallResult()
2841 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); in LowerCallResult()
2843 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; in LowerCallResult()
2845 Shift, DL, VA.getLocVT(), Val, in LowerCallResult()
2846 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); in LowerCallResult()
2849 switch (VA.getLocInfo()) { in LowerCallResult()
2855 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); in LowerCallResult()
2859 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); in LowerCallResult()
2863 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, in LowerCallResult()
2864 DAG.getValueType(VA.getValVT())); in LowerCallResult()
2865 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); in LowerCallResult()
2869 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, in LowerCallResult()
2870 DAG.getValueType(VA.getValVT())); in LowerCallResult()
2871 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); in LowerCallResult()
2881 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, in UnpackFromArgumentSlot() argument
2883 MVT LocVT = VA.getLocVT(); in UnpackFromArgumentSlot()
2884 EVT ValVT = VA.getValVT(); in UnpackFromArgumentSlot()
2887 switch (VA.getLocInfo()) { in UnpackFromArgumentSlot()
2894 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); in UnpackFromArgumentSlot()
2896 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; in UnpackFromArgumentSlot()
2898 Opcode, DL, VA.getLocVT(), Val, in UnpackFromArgumentSlot()
2899 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); in UnpackFromArgumentSlot()
2908 switch (VA.getLocInfo()) { in UnpackFromArgumentSlot()
2977 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments() local
2982 EVT ValVT = VA.getValVT(); in LowerFormalArguments()
2984 bool IsRegLoc = VA.isRegLoc(); in LowerFormalArguments()
2996 FirstByValReg, LastByValReg, VA, CCInfo); in LowerFormalArguments()
3003 MVT RegVT = VA.getLocVT(); in LowerFormalArguments()
3004 unsigned ArgReg = VA.getLocReg(); in LowerFormalArguments()
3012 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); in LowerFormalArguments()
3033 MVT LocVT = VA.getLocVT(); in LowerFormalArguments()
3040 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat()) in LowerFormalArguments()
3041 LocVT = VA.getValVT(); in LowerFormalArguments()
3045 assert(VA.isMemLoc()); in LowerFormalArguments()
3049 VA.getLocMemOffset(), true); in LowerFormalArguments()
3059 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); in LowerFormalArguments()
3153 CCValAssign &VA = RVLocs[i]; in LowerReturn() local
3154 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
3157 switch (VA.getLocInfo()) { in LowerReturn()
3163 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val); in LowerReturn()
3169 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val); in LowerReturn()
3175 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val); in LowerReturn()
3181 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val); in LowerReturn()
3187 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); in LowerReturn()
3189 ISD::SHL, DL, VA.getLocVT(), Val, in LowerReturn()
3190 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); in LowerReturn()
3193 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); in LowerReturn()
3197 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
3646 const CCValAssign &VA, MipsCCState &State) const { in copyByValRegs() argument
3661 FrameObjOffset = VA.getLocMemOffset(); in copyByValRegs()
3696 const CCValAssign &VA) const { in passByValArg()
3779 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL)); in passByValArg()