Lines Matching refs:Subtarget
59 : TargetLowering(TM), Subtarget(STI) { in PPCTargetLowering()
66 bool isPPC64 = Subtarget.isPPC64(); in PPCTargetLowering()
71 if (!Subtarget.useSoftFloat()) { in PPCTargetLowering()
100 if (Subtarget.useCRBits()) { in PPCTargetLowering()
103 if (isPPC64 || Subtarget.hasFPCVT()) { in PPCTargetLowering()
177 if (!Subtarget.hasFSQRT() && in PPCTargetLowering()
178 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() && in PPCTargetLowering()
179 Subtarget.hasFRE())) in PPCTargetLowering()
182 if (!Subtarget.hasFSQRT() && in PPCTargetLowering()
183 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() && in PPCTargetLowering()
184 Subtarget.hasFRES())) in PPCTargetLowering()
187 if (Subtarget.hasFCPSGN()) { in PPCTargetLowering()
195 if (Subtarget.hasFPRND()) { in PPCTargetLowering()
217 if (Subtarget.hasPOPCNTD()) { in PPCTargetLowering()
229 if (!Subtarget.useCRBits()) { in PPCTargetLowering()
242 if (!Subtarget.useCRBits()) in PPCTargetLowering()
246 if (!Subtarget.useCRBits()) in PPCTargetLowering()
258 if (Subtarget.hasDirectMove()) { in PPCTargetLowering()
305 if (Subtarget.isSVR4ABI()) { in PPCTargetLowering()
325 if (Subtarget.isSVR4ABI() && !isPPC64) in PPCTargetLowering()
360 if (Subtarget.has64BitSupport()) { in PPCTargetLowering()
370 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) in PPCTargetLowering()
378 if (Subtarget.hasFPCVT()) { in PPCTargetLowering()
379 if (Subtarget.has64BitSupport()) { in PPCTargetLowering()
392 if (Subtarget.use64BitRegs()) { in PPCTargetLowering()
408 if (Subtarget.hasAltivec()) { in PPCTargetLowering()
417 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) { in PPCTargetLowering()
507 Subtarget.useCRBits() ? Legal : Expand); in PPCTargetLowering()
526 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) { in PPCTargetLowering()
531 if (Subtarget.hasP8Altivec()) in PPCTargetLowering()
553 if (Subtarget.hasVSX()) { in PPCTargetLowering()
556 if (Subtarget.hasP8Vector()) { in PPCTargetLowering()
560 if (Subtarget.hasDirectMove()) { in PPCTargetLowering()
603 if (Subtarget.hasP8Vector()) in PPCTargetLowering()
612 if (Subtarget.hasP8Altivec()) { in PPCTargetLowering()
653 if (Subtarget.hasP8Altivec()) { in PPCTargetLowering()
659 if (Subtarget.hasQPX()) { in PPCTargetLowering()
674 if (!Subtarget.useCRBits()) in PPCTargetLowering()
724 if (!Subtarget.useCRBits()) in PPCTargetLowering()
763 if (!Subtarget.useCRBits()) in PPCTargetLowering()
815 if (Subtarget.has64BitSupport()) in PPCTargetLowering()
827 if (Subtarget.hasAltivec()) { in PPCTargetLowering()
843 if (Subtarget.hasFPCVT()) in PPCTargetLowering()
848 if (Subtarget.useCRBits()) in PPCTargetLowering()
859 if (Subtarget.useCRBits()) { in PPCTargetLowering()
872 if (Subtarget.isDarwin()) { in PPCTargetLowering()
887 if (Subtarget.useCRBits()) { in PPCTargetLowering()
893 if (Subtarget.isDarwin()) in PPCTargetLowering()
896 switch (Subtarget.getDarwinDirective()) { in PPCTargetLowering()
916 if (Subtarget.enableMachineScheduler()) in PPCTargetLowering()
925 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc || in PPCTargetLowering()
926 Subtarget.getDarwinDirective() == PPC::DIR_E5500) { in PPCTargetLowering()
933 } else if (Subtarget.getDarwinDirective() == PPC::DIR_A2) { in PPCTargetLowering()
976 if (Subtarget.isDarwin()) in getByValTypeAlignment()
981 unsigned Align = Subtarget.isPPC64() ? 8 : 4; in getByValTypeAlignment()
982 if (Subtarget.hasAltivec() || Subtarget.hasQPX()) in getByValTypeAlignment()
983 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16); in getByValTypeAlignment()
988 return Subtarget.useSoftFloat(); in useSoftFloat()
1085 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32; in getSetCCResultType()
1087 if (Subtarget.hasQPX()) in getSetCCResultType()
1197 const PPCSubtarget& Subtarget = in isVPKUDUMShuffleMask() local
1199 if (!Subtarget.hasP8Vector()) in isVPKUDUMShuffleMask()
1806 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectAddressRegImm()
1858 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectAddressRegRegOnly()
1892 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) { in getPreIndexedAddressParts()
1956 const PPCSubtarget &Subtarget, in GetLabelAccessInfo() argument
1972 if (GV && Subtarget.hasLazyResolverStub(GV)) { in GetLabelAccessInfo()
2034 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) { in LowerConstantPool()
2042 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag); in LowerConstantPool()
2044 if (isPIC && Subtarget.isSVR4ABI()) { in LowerConstantPool()
2063 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) { in LowerJumpTable()
2071 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag); in LowerJumpTable()
2073 if (isPIC && Subtarget.isSVR4ABI()) { in LowerJumpTable()
2092 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) { in LowerBlockAddress()
2100 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag); in LowerBlockAddress()
2120 bool is64bit = Subtarget.isPPC64(); in LowerGlobalTLSAddress()
2205 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) { in LowerGlobalAddress()
2213 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag, GV); in LowerGlobalAddress()
2215 if (isPIC && Subtarget.isSVR4ABI()) { in LowerGlobalAddress()
2302 const PPCSubtarget &Subtarget) const { in LowerVAARG()
2311 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only"); in LowerVAARG()
2410 const PPCSubtarget &Subtarget) const { in LowerVACOPY()
2411 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only"); in LowerVACOPY()
2464 const PPCSubtarget &Subtarget) const { in LowerVASTART()
2470 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) { in LowerVASTART()
2773 if (Subtarget.isSVR4ABI()) { in LowerFormalArguments()
2774 if (Subtarget.isPPC64()) in LowerFormalArguments()
2840 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in LowerFormalArguments_32SVR4()
2861 if (Subtarget.hasP8Vector()) in LowerFormalArguments_32SVR4()
2867 if (Subtarget.hasVSX()) in LowerFormalArguments_32SVR4()
2878 RC = Subtarget.hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass; in LowerFormalArguments_32SVR4()
2938 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea); in LowerFormalArguments_32SVR4()
2958 if (Subtarget.useSoftFloat()) in LowerFormalArguments_32SVR4()
3046 bool isELFv2ABI = Subtarget.isELFv2ABI(); in LowerFormalArguments_64SVR4()
3047 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerFormalArguments_64SVR4()
3060 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in LowerFormalArguments_64SVR4()
3098 Subtarget.hasQPX())) in LowerFormalArguments_64SVR4()
3295 Subtarget.hasP8Vector() in LowerFormalArguments_64SVR4()
3299 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() in LowerFormalArguments_64SVR4()
3347 if (!Subtarget.hasQPX()) { in LowerFormalArguments_64SVR4()
3424 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea); in LowerFormalArguments_64SVR4()
3478 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in LowerFormalArguments_Darwin()
3784 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea); in LowerFormalArguments_Darwin()
3998 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in EmitTailCallLoadFPAndRetAddr()
4106 ImmutableCallSite *CS, const PPCSubtarget &Subtarget) { in PrepareCall() argument
4108 bool isPPC64 = Subtarget.isPPC64(); in PrepareCall()
4109 bool isSVR4ABI = Subtarget.isSVR4ABI(); in PrepareCall()
4110 bool isELFv2ABI = Subtarget.isELFv2ABI(); in PrepareCall()
4132 (Subtarget.getTargetTriple().isMacOSX() && in PrepareCall()
4133 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) && in PrepareCall()
4135 (Subtarget.isTargetELF() && !isPPC64 && in PrepareCall()
4156 (Subtarget.getTargetTriple().isMacOSX() && in PrepareCall()
4157 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) || in PrepareCall()
4158 (Subtarget.isTargetELF() && !isPPC64 && in PrepareCall()
4220 bool LoadsInv = Subtarget.hasInvariantFunctionDescriptors(); in PrepareCall()
4374 RegsToPass, Ops, NodeTys, CS, Subtarget); in FinishCall()
4377 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64()) in FinishCall()
4388 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); in FinishCall()
4419 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() && in FinishCall()
4435 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset(); in FinishCall()
4486 if (Subtarget.isSVR4ABI()) { in LowerCall()
4487 if (Subtarget.isPPC64()) in LowerCall()
4541 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(), in LowerCall_32SVR4()
4755 bool isELFv2ABI = Subtarget.isELFv2ABI(); in LowerCall_64SVR4()
4756 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerCall_64SVR4()
4781 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in LowerCall_64SVR4()
4841 if (Subtarget.hasQPX()) { in LowerCall_64SVR4()
4882 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes); in LowerCall_64SVR4()
5205 if (!Subtarget.hasQPX()) { in LowerCall_64SVR4()
5342 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset(); in LowerCall_64SVR4()
5405 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); in LowerCall_Darwin()
5450 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes); in LowerCall_Darwin()
5827 SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const { in LowerGET_DYNAMIC_AREA_OFFSET()
5843 const PPCSubtarget &Subtarget) const { in LowerSTACKRESTORE()
5851 bool isPPC64 = Subtarget.isPPC64(); in LowerSTACKRESTORE()
5874 bool isPPC64 = Subtarget.isPPC64(); in getReturnAddrFrameIndex()
5885 int LROffset = Subtarget.getFrameLowering()->getReturnSaveOffset(); in getReturnAddrFrameIndex()
5897 bool isPPC64 = Subtarget.isPPC64(); in getFramePointerFrameIndex()
5908 int FPOffset = Subtarget.getFrameLowering()->getFramePointerSaveOffset(); in getFramePointerFrameIndex()
5919 const PPCSubtarget &Subtarget) const { in LowerDYNAMIC_STACKALLOC()
6129 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ), in LowerFP_TO_INTForReuse()
6133 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) && in LowerFP_TO_INTForReuse()
6142 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() && in LowerFP_TO_INTForReuse()
6143 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()); in LowerFP_TO_INTForReuse()
6194 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ), in LowerFP_TO_INTDirectMove()
6199 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) && in LowerFP_TO_INTDirectMove()
6212 if (Subtarget.hasDirectMove() && Subtarget.isPPC64()) in LowerFP_TO_INT()
6301 assert(Subtarget.hasFPCVT() && in LowerINT_TO_FPDirectMove()
6328 if (Subtarget.hasQPX() && Op.getOperand(0).getValueType() == MVT::v4i1) { in LowerINT_TO_FP()
6362 if (Subtarget.hasDirectMove() && Subtarget.isPPC64() && Subtarget.hasFPCVT()) in LowerINT_TO_FP()
6365 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) && in LowerINT_TO_FP()
6370 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in LowerINT_TO_FP()
6375 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in LowerINT_TO_FP()
6392 !Subtarget.hasFPCVT() && in LowerINT_TO_FP()
6436 } else if (Subtarget.hasLFIWAX() && in LowerINT_TO_FP()
6446 } else if (Subtarget.hasFPCVT() && in LowerINT_TO_FP()
6456 } else if (((Subtarget.hasLFIWAX() && in LowerINT_TO_FP()
6458 (Subtarget.hasFPCVT() && in LowerINT_TO_FP()
6494 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) in LowerINT_TO_FP()
6511 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) { in LowerINT_TO_FP()
6545 assert(Subtarget.isPPC64() && in LowerINT_TO_FP()
6569 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) in LowerINT_TO_FP()
6812 if (Subtarget.hasQPX() && Op.getValueType() == MVT::v4i1) { in LowerBUILD_VECTOR()
6930 if (Subtarget.hasQPX()) in LowerBUILD_VECTOR()
6938 HasAnyUndefs, 0, !Subtarget.isLittleEndian()) || in LowerBUILD_VECTOR()
7068 unsigned Amt = Subtarget.isLittleEndian() ? 15 : 1; in LowerBUILD_VECTOR()
7074 unsigned Amt = Subtarget.isLittleEndian() ? 14 : 2; in LowerBUILD_VECTOR()
7080 unsigned Amt = Subtarget.isLittleEndian() ? 13 : 3; in LowerBUILD_VECTOR()
7176 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerVECTOR_SHUFFLE()
7178 if (Subtarget.hasQPX()) { in LowerVECTOR_SHUFFLE()
7233 (Subtarget.hasP8Altivec() && ( in LowerVECTOR_SHUFFLE()
7254 (Subtarget.hasP8Altivec() && ( in LowerVECTOR_SHUFFLE()
7357 bool &isDot, const PPCSubtarget &Subtarget) { in getVectorCompareInfo() argument
7371 if (Subtarget.hasP8Altivec()) { in getVectorCompareInfo()
7384 if (Subtarget.hasP8Altivec()) { in getVectorCompareInfo()
7395 if (Subtarget.hasP8Altivec()) { in getVectorCompareInfo()
7409 if (Subtarget.hasVSX()) { in getVectorCompareInfo()
7432 if (Subtarget.hasP8Altivec()) { in getVectorCompareInfo()
7445 if (Subtarget.hasP8Altivec()) { in getVectorCompareInfo()
7456 if (Subtarget.hasP8Altivec()) { in getVectorCompareInfo()
7476 if (!getVectorCompareInfo(Op, CompareOpc, isDot, Subtarget)) in LowerINTRINSIC_WO_CHAIN()
7638 if (!Subtarget.useCRBits()) in LowerEXTRACT_VECTOR_ELT()
7912 bool isLittleEndian = Subtarget.isLittleEndian(); in LowerMUL()
7961 return LowerVASTART(Op, DAG, Subtarget); in LowerOperation()
7964 return LowerVAARG(Op, DAG, Subtarget); in LowerOperation()
7967 return LowerVACOPY(Op, DAG, Subtarget); in LowerOperation()
7969 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget); in LowerOperation()
7971 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget); in LowerOperation()
7972 case ISD::GET_DYNAMIC_AREA_OFFSET: return LowerGET_DYNAMIC_AREA_OFFSET(Op, DAG, Subtarget); in LowerOperation()
8045 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64()) in ReplaceNodeResults()
8051 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget); in ReplaceNodeResults()
8126 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in EmitAtomicBinary()
8136 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4"); in EmitAtomicBinary()
8141 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4"); in EmitAtomicBinary()
8211 if (Subtarget.hasPartwordAtomics()) in EmitPartwordAtomicBinary()
8215 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in EmitPartwordAtomicBinary()
8220 bool is64bit = Subtarget.isPPC64(); in EmitPartwordAtomicBinary()
8341 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitEHSjLjSetJmp()
8412 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) { in emitEHSjLjSetJmp()
8425 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1; in emitEHSjLjSetJmp()
8427 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP; in emitEHSjLjSetJmp()
8430 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW)) in emitEHSjLjSetJmp()
8438 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo(); in emitEHSjLjSetJmp()
8454 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg); in emitEHSjLjSetJmp()
8457 if (Subtarget.isPPC64()) { in emitEHSjLjSetJmp()
8488 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in emitEHSjLjLongJmp()
8510 : (Subtarget.isSVR4ABI() && in emitEHSjLjLongJmp()
8575 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) { in emitEHSjLjLongJmp()
8598 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI() && in EmitInstrWithCustomInserter()
8620 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in EmitInstrWithCustomInserter()
8629 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 || in EmitInstrWithCustomInserter()
8839 (Subtarget.hasPartwordAtomics() && in EmitInstrWithCustomInserter()
8841 (Subtarget.hasPartwordAtomics() && in EmitInstrWithCustomInserter()
8853 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics."); in EmitInstrWithCustomInserter()
8858 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics."); in EmitInstrWithCustomInserter()
8936 bool is64bit = Subtarget.isPPC64(); in EmitInstrWithCustomInserter()
9160 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) || in getRsqrtEstimate()
9161 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) || in getRsqrtEstimate()
9162 (VT == MVT::v4f32 && Subtarget.hasAltivec()) || in getRsqrtEstimate()
9163 (VT == MVT::v2f64 && Subtarget.hasVSX()) || in getRsqrtEstimate()
9164 (VT == MVT::v4f32 && Subtarget.hasQPX()) || in getRsqrtEstimate()
9165 (VT == MVT::v4f64 && Subtarget.hasQPX())) { in getRsqrtEstimate()
9182 if ((VT == MVT::f32 && Subtarget.hasFRES()) || in getRecipEstimate()
9183 (VT == MVT::f64 && Subtarget.hasFRE()) || in getRecipEstimate()
9184 (VT == MVT::v4f32 && Subtarget.hasAltivec()) || in getRecipEstimate()
9185 (VT == MVT::v2f64 && Subtarget.hasVSX()) || in getRecipEstimate()
9186 (VT == MVT::v4f32 && Subtarget.hasQPX()) || in getRecipEstimate()
9187 (VT == MVT::v4f64 && Subtarget.hasQPX())) { in getRecipEstimate()
9210 switch (Subtarget.getDarwinDirective()) { in combineRepeatedFPDivisors()
9448 assert(Subtarget.useCRBits() && "Expecting to be tracking CR bits"); in DAGCombineTruncBoolExt()
9744 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) || in DAGCombineExtBoolTrunc()
9745 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64()))) in DAGCombineExtBoolTrunc()
10006 if (!Subtarget.has64BitSupport()) in combineFPToIntToFP()
10026 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) && in combineFPToIntToFP()
10031 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in combineFPToIntToFP()
10036 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in combineFPToIntToFP()
10043 Subtarget.hasFPCVT()) || in combineFPToIntToFP()
10061 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) { in combineFPToIntToFP()
10208 if (Subtarget.hasSTFIWX() && !cast<StoreSDNode>(N)->isTruncatingStore() && in PerformDAGCombine()
10239 (Subtarget.hasLDBRX() && Subtarget.isPPC64() && in PerformDAGCombine()
10260 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() && in PerformDAGCombine()
10274 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() && in PerformDAGCombine()
10286 ((Subtarget.hasAltivec() && ISD::isNON_EXTLoad(N) && in PerformDAGCombine()
10288 !Subtarget.hasP8Vector() && (VT == MVT::v16i8 || VT == MVT::v8i16 || in PerformDAGCombine()
10290 (Subtarget.hasQPX() && (VT == MVT::v4f64 || VT == MVT::v4f32) && in PerformDAGCombine()
10296 bool isLittleEndian = Subtarget.isLittleEndian(); in PerformDAGCombine()
10324 if (Subtarget.hasAltivec()) { in PerformDAGCombine()
10412 Perm = Subtarget.hasAltivec() ? in PerformDAGCombine()
10427 bool isLittleEndian = Subtarget.isLittleEndian(); in PerformDAGCombine()
10486 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) { in PerformDAGCombine()
10499 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) { in PerformDAGCombine()
10515 (Subtarget.hasLDBRX() && Subtarget.isPPC64() && in PerformDAGCombine()
10663 getVectorCompareInfo(LHS, CompareOpc, isDot, Subtarget)) { in PerformDAGCombine()
10724 if (VT == MVT::i64 && !Subtarget.isPPC64()) in BuildSDIVPow2()
10795 switch (Subtarget.getDarwinDirective()) { in getPrefLoopAlignment()
10808 const PPCInstrInfo *TII = Subtarget.getInstrInfo(); in getPrefLoopAlignment()
10924 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
10928 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
10936 if (VT == MVT::v4f64 && Subtarget.hasQPX()) in getRegForInlineAsmConstraint()
10938 if (VT == MVT::v4f32 && Subtarget.hasQPX()) in getRegForInlineAsmConstraint()
10942 if (VT == MVT::v4f64 && Subtarget.hasQPX()) in getRegForInlineAsmConstraint()
10944 if (VT == MVT::v4f32 && Subtarget.hasQPX()) in getRegForInlineAsmConstraint()
10946 if (Subtarget.hasAltivec()) in getRegForInlineAsmConstraint()
10951 } else if (Constraint == "wc" && Subtarget.useCRBits()) { in getRegForInlineAsmConstraint()
10955 Constraint == "wf") && Subtarget.hasVSX()) { in getRegForInlineAsmConstraint()
10957 } else if (Constraint == "ws" && Subtarget.hasVSX()) { in getRegForInlineAsmConstraint()
10958 if (VT == MVT::f32 && Subtarget.hasP8Vector()) in getRegForInlineAsmConstraint()
10973 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() && in getRegForInlineAsmConstraint()
11119 bool isPPC64 = Subtarget.isPPC64(); in LowerRETURNADDR()
11125 DAG.getConstant(Subtarget.getFrameLowering()->getReturnSaveOffset(), dl, in LowerRETURNADDR()
11171 bool isPPC64 = Subtarget.isPPC64(); in getRegisterByName()
11172 bool isDarwinABI = Subtarget.isDarwinABI(); in getRegisterByName()
11409 if (Subtarget.hasQPX() && Size >= 32 && (!IsMemset || Size >= 64) && in getOptimalMemOpType()
11417 if (Subtarget.hasAltivec() && Size >= 16 && in getOptimalMemOpType()
11419 ((IsMemset && Subtarget.hasVSX()) || Subtarget.hasP8Vector()))) in getOptimalMemOpType()
11423 if (Subtarget.isPPC64()) { in getOptimalMemOpType()
11464 (Subtarget.isPPC64() && MemVT == MVT::i32)) && in isZExtFree()
11508 if (Subtarget.hasVSX()) { in allowsMisalignedMemoryAccesses()
11558 return Subtarget.isPPC64() ? PPC::X3 : PPC::R3; in getExceptionPointerRegister()
11563 return Subtarget.isPPC64() ? PPC::X4 : PPC::R4; in getExceptionSelectorRegister()
11570 return Subtarget.hasDirectMove(); // Don't need stack ops with direct moves in shouldExpandBuildVectorWithShuffles()
11572 if (Subtarget.hasQPX()) { in shouldExpandBuildVectorWithShuffles()
11581 if (DisableILPPref || Subtarget.enableMachineScheduler()) in getSchedulingPreference()