Lines Matching refs:VA
231 CCValAssign &VA = RVLocs[i]; in LowerReturn_32() local
232 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_32()
236 if (VA.needsCustom()) { in LowerReturn_32()
237 assert(VA.getLocVT() == MVT::v2i32); in LowerReturn_32()
248 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Flag); in LowerReturn_32()
250 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
251 VA = RVLocs[++i]; // skip ahead to next loc in LowerReturn_32()
252 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1, in LowerReturn_32()
255 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag); in LowerReturn_32()
259 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
314 CCValAssign &VA = RVLocs[i]; in LowerReturn_64() local
315 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_64()
319 switch (VA.getLocInfo()) { in LowerReturn_64()
322 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
325 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
328 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
336 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { in LowerReturn_64()
342 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerReturn_64()
350 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); in LowerReturn_64()
354 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_64()
407 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments_32() local
422 if (VA.isRegLoc()) { in LowerFormalArguments_32()
423 if (VA.needsCustom()) { in LowerFormalArguments_32()
424 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32); in LowerFormalArguments_32()
427 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); in LowerFormalArguments_32()
452 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), WholeValue); in LowerFormalArguments_32()
457 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments_32()
459 if (VA.getLocVT() == MVT::f32) in LowerFormalArguments_32()
461 else if (VA.getLocVT() != MVT::i32) { in LowerFormalArguments_32()
463 DAG.getValueType(VA.getLocVT())); in LowerFormalArguments_32()
464 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg); in LowerFormalArguments_32()
470 assert(VA.isMemLoc()); in LowerFormalArguments_32()
472 unsigned Offset = VA.getLocMemOffset()+StackOffset; in LowerFormalArguments_32()
475 if (VA.needsCustom()) { in LowerFormalArguments_32()
476 assert(VA.getValVT() == MVT::f64 || MVT::v2i32); in LowerFormalArguments_32()
483 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, in LowerFormalArguments_32()
511 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), WholeValue); in LowerFormalArguments_32()
521 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) { in LowerFormalArguments_32()
522 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, in LowerFormalArguments_32()
525 } else if (VA.getValVT() == MVT::f128) { in LowerFormalArguments_32()
612 CCValAssign &VA = ArgLocs[i]; in LowerFormalArguments_64() local
613 if (VA.isRegLoc()) { in LowerFormalArguments_64()
618 unsigned VReg = MF.addLiveIn(VA.getLocReg(), in LowerFormalArguments_64()
619 getRegClassFor(VA.getLocVT())); in LowerFormalArguments_64()
620 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT()); in LowerFormalArguments_64()
623 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) in LowerFormalArguments_64()
624 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
629 switch (VA.getLocInfo()) { in LowerFormalArguments_64()
631 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
632 DAG.getValueType(VA.getValVT())); in LowerFormalArguments_64()
635 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
636 DAG.getValueType(VA.getValVT())); in LowerFormalArguments_64()
643 if (VA.isExtInLoc()) in LowerFormalArguments_64()
644 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg); in LowerFormalArguments_64()
651 assert(VA.isMemLoc()); in LowerFormalArguments_64()
654 unsigned Offset = VA.getLocMemOffset() + ArgArea; in LowerFormalArguments_64()
655 unsigned ValSize = VA.getValVT().getSizeInBits() / 8; in LowerFormalArguments_64()
659 if (VA.isExtInLoc()) in LowerFormalArguments_64()
663 VA.getValVT(), DL, Chain, in LowerFormalArguments_64()
800 CCValAssign &VA = ArgLocs[i]; in LowerCall_32() local
810 switch (VA.getLocInfo()) { in LowerCall_32()
814 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
817 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
820 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
823 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall_32()
828 assert(VA.needsCustom()); in LowerCall_32()
840 if (VA.needsCustom()) { in LowerCall_32()
841 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32); in LowerCall_32()
843 if (VA.isMemLoc()) { in LowerCall_32()
844 unsigned Offset = VA.getLocMemOffset() + StackOffset; in LowerCall_32()
857 if (VA.getLocVT() == MVT::f64) { in LowerCall_32()
875 if (VA.isRegLoc()) { in LowerCall_32()
876 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Part0)); in LowerCall_32()
892 unsigned Offset = VA.getLocMemOffset() + StackOffset; in LowerCall_32()
912 if (VA.isRegLoc()) { in LowerCall_32()
913 if (VA.getLocVT() != MVT::f32) { in LowerCall_32()
914 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall_32()
918 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall_32()
922 assert(VA.isMemLoc()); in LowerCall_32()
926 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + StackOffset, in LowerCall_32()
1067 const CCValAssign &VA = ArgLocs[i]; in fixupVariableFloatArgs() local
1068 MVT ValTy = VA.getLocVT(); in fixupVariableFloatArgs()
1071 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128)) in fixupVariableFloatArgs()
1074 if (Outs[VA.getValNo()].IsFixed) in fixupVariableFloatArgs()
1083 unsigned Offset = argSize * (VA.getLocReg() - firstReg); in fixupVariableFloatArgs()
1091 NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(), in fixupVariableFloatArgs()
1097 NewVA = CCValAssign::getCustomReg(VA.getValNo(), VA.getValVT(), in fixupVariableFloatArgs()
1102 NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(), in fixupVariableFloatArgs()
1103 Offset, VA.getLocVT(), VA.getLocInfo()); in fixupVariableFloatArgs()
1157 const CCValAssign &VA = ArgLocs[i]; in LowerCall_64() local
1161 switch (VA.getLocInfo()) { in LowerCall_64()
1167 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()
1170 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()
1173 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()
1178 if (!VA.needsCustom() || VA.getValVT() != MVT::f128 in LowerCall_64()
1179 || VA.getLocVT() != MVT::i128) in LowerCall_64()
1180 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); in LowerCall_64()
1184 if (VA.isRegLoc()) { in LowerCall_64()
1185 if (VA.needsCustom() && VA.getValVT() == MVT::f128 in LowerCall_64()
1186 && VA.getLocVT() == MVT::i128) { in LowerCall_64()
1188 unsigned Offset = 8 * (VA.getLocReg() - SP::I0); in LowerCall_64()
1207 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), in LowerCall_64()
1209 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()+1), in LowerCall_64()
1216 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { in LowerCall_64()
1223 ArgLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerCall_64()
1231 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg)); in LowerCall_64()
1235 assert(VA.isMemLoc()); in LowerCall_64()
1241 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + in LowerCall_64()
1326 CCValAssign &VA = RVLocs[i]; in LowerCall_64() local
1327 unsigned Reg = toCallerWindow(VA.getLocReg()); in LowerCall_64()
1345 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) in LowerCall_64()
1346 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV, in LowerCall_64()
1351 switch (VA.getLocInfo()) { in LowerCall_64()
1353 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, in LowerCall_64()
1354 DAG.getValueType(VA.getValVT())); in LowerCall_64()
1357 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, in LowerCall_64()
1358 DAG.getValueType(VA.getValVT())); in LowerCall_64()
1365 if (VA.isExtInLoc()) in LowerCall_64()
1366 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV); in LowerCall_64()