Lines Matching refs:ZERO_EXTEND
749 setOperationAction(ISD::ZERO_EXTEND, VT, Expand); in X86TargetLowering()
1139 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom); in X86TargetLowering()
1140 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom); in X86TargetLowering()
1141 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom); in X86TargetLowering()
1444 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom); in X86TargetLowering()
1445 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom); in X86TargetLowering()
1649 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom); in X86TargetLowering()
1651 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom); in X86TargetLowering()
1655 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom); in X86TargetLowering()
1816 setTargetDAGCombine(ISD::ZERO_EXTEND); in X86TargetLowering()
2223 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
2364 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) in getTypeForExtArgOrReturn()
3199 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); in LowerCall()
3466 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee); in LowerCall()
5135 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, in LowerBuildVectorv16i8()
5139 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); in LowerBuildVectorv16i8()
6390 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); in LowerBUILD_VECTOR()
7982 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S); in lowerVectorShuffleAsElementInsertion()
11563 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec); in ExtractBitFromMaskVector()
11709 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec), in InsertBitToMaskVector()
11710 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx); in InsertBitToMaskVector()
12862 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0)); in lowerUINT_TO_FP_vec()
12871 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0)); in lowerUINT_TO_FP_vec()
13138 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32); in FP_TO_INTHelper()
13169 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In); in LowerAVXExtend()
13194 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND; in LowerAVXExtend()
13764 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op); in EmitTest()
14013 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; in EmitCmp()
16070 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND && in getTargetVShiftNode()
16674 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); in LowerINTRINSIC_WO_CHAIN()
16692 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); in LowerINTRINSIC_WO_CHAIN()
16819 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); in LowerINTRINSIC_WO_CHAIN()
16829 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); in LowerINTRINSIC_WO_CHAIN()
16893 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); in LowerINTRINSIC_WO_CHAIN()
17286 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC); in LowerINTRINSIC_W_CHAIN()
17745 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); in LowerFLT_ROUNDS_()
17799 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, NewVT, Op.getOperand(0)); in LowerVectorCTLZ_AVX512()
17821 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); in LowerCTLZ()
17860 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); in LowerCTLZ_ZERO_UNDEF()
18528 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt); in LowerScalarVariableShift()
18530 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt); in LowerScalarVariableShift()
18894 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerShift()
20082 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG); in LowerOperation()
20253 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64, in ReplaceNodeResults()
23835 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) in PerformEXTRACT_VECTOR_ELTCombine()
24162 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); in PerformSELECTCombine()
24176 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, in PerformSELECTCombine()
24211 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), in PerformSELECTCombine()
24530 while (SetCC.getOpcode() == ISD::ZERO_EXTEND || in checkBoolTestSetCCCombine()
24575 if (Op.getOpcode() == ISD::ZERO_EXTEND || in checkBoolTestSetCCCombine()
24708 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); in PerformCMOVCombine()
24725 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, in PerformCMOVCombine()
24762 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), in PerformCMOVCombine()
24981 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND || in PerformSHLCombine()
25152 case ISD::ZERO_EXTEND: in CMPEQCombine()
25177 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0), in CMPEQCombine()
25258 N->getOpcode() == ISD::ZERO_EXTEND || in WidenMaskArithmetic()
25300 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getVectorElementType(), in WidenMaskArithmetic()
25314 case ISD::ZERO_EXTEND: { in WidenMaskArithmetic()
25859 Operands[0].getOpcode() == ISD::ZERO_EXTEND && in detectAVGPattern()
25888 if (Operands[j].getOpcode() != ISD::ZERO_EXTEND || in detectAVGPattern()
27443 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0); in PerformUINT_TO_FPCombine()
27534 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) in OptimizeConditionalInDecrement()
27722 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget); in PerformDAGCombine()
27769 case ISD::ZERO_EXTEND: in isTypeDesirableForOp()
27813 case ISD::ZERO_EXTEND: in IsDesirableToPromoteOp()