Lines Matching refs:getSizeInBits
1576 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); in X86TargetLowering()
2020 switch (VT.getSizeInBits()) { in allowsMisalignedMemoryAccesses()
2584 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, in LowerMemArgument()
3341 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; in LowerCall()
3621 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; in MatchingStackOffset()
4251 unsigned ElSize = VT.getVectorElementType().getSizeInBits(); in isVEXTRACTIndex()
4269 unsigned ElSize = VT.getVectorElementType().getSizeInBits(); in isVINSERTIndex()
4302 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits(); in getExtractVEXTRACTImmediate()
4317 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits(); in getInsertVINSERTImmediate()
4439 unsigned Factor = VT.getSizeInBits()/vectorWidth; in ExtractSubVector()
4448 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits(); in ExtractSubVector()
4497 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits(); in InsertSubVector()
4535 unsigned ScalarSize = ScalarType.getSizeInBits(); in Insert128BitVector()
4590 IdxVal % SubVecVT.getSizeInBits() == 0 && in Insert1BitVector()
4808 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8; in getTargetShuffleMask()
5337 unsigned RequiredAlign = VT.getSizeInBits()/8; in LowerAsSplatVectorLoad()
5423 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems) in EltsFromConsecutiveLoads()
5425 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i)) in EltsFromConsecutiveLoads()
5438 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems) in EltsFromConsecutiveLoads()
5467 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) && in EltsFromConsecutiveLoads()
5560 if (VT.getSizeInBits() >= 256) in LowerVectorBroadcast()
5575 Ld.getValueType().getSizeInBits() >= 32; in LowerVectorBroadcast()
5583 unsigned ScalarSize = Ld.getValueType().getSizeInBits(); in LowerVectorBroadcast()
5584 bool IsGE256 = (VT.getSizeInBits() >= 256); in LowerVectorBroadcast()
5775 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8)); in ConvertI1VectorToInteger()
5801 if (Imm.getValueSizeInBits() == VT.getSizeInBits()) in LowerBUILD_VECTORvXi1()
5840 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8)); in LowerBUILD_VECTORvXi1()
5847 if (Imm.getValueSizeInBits() == VT.getSizeInBits()) in LowerBUILD_VECTORvXi1()
6311 unsigned EVTBits = ExtVT.getSizeInBits(); in LowerBUILD_VECTOR()
6415 unsigned NumBits = VT.getSizeInBits(); in LowerBUILD_VECTOR()
6689 if (ResVT.getSizeInBits() >= 16) in LowerCONCAT_VECTORSvXi1()
6969 int NumEltBits = EltVT.getSizeInBits(); in lowerVectorShuffleAsBitMask()
7013 int NumEltBits = EltVT.getSizeInBits(); in lowerVectorShuffleAsBitBlend()
7027 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64); in lowerVectorShuffleAsBitBlend()
7115 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32; in lowerVectorShuffleAsBlend()
7164 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8); in lowerVectorShuffleAsBlend()
7295 int NumLanes = VT.getSizeInBits() / 128; in lowerVectorShuffleAsByteRotate()
7793 int Bits = VT.getSizeInBits(); in lowerVectorShuffleAsZeroOrAnyExtend()
7925 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits()) in getScalarValueForVectorElement()
8037 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL, in lowerVectorShuffleAsElementInsertion()
8067 const unsigned EltSize = EltVT.getSizeInBits(); in lowerVectorShuffleAsTruncBroadcast()
8068 const unsigned V0EltSize = V0EltVT.getSizeInBits(); in lowerVectorShuffleAsTruncBroadcast()
9963 assert(VT.getSizeInBits() >= 256 && in splitAndLowerVectorShuffle()
10125 int LaneCount = VT.getSizeInBits() / 128; in lowerVectorShuffleAsSplitOrBlend()
10331 VT.getSizeInBits() / 64); in lowerVectorShuffleByMerging128BitLanes()
11249 assert((VT.getSizeInBits() != 64 || Is1BitVector) && in lowerVectorShuffle()
11494 if (VT.getSizeInBits() == 8) { in LowerEXTRACT_VECTOR_ELT_SSE4()
11502 if (VT.getSizeInBits() == 16) { in LowerEXTRACT_VECTOR_ELT_SSE4()
11596 VecVT.getVectorElementType().getSizeInBits() == 32)) { in LowerEXTRACT_VECTOR_ELT()
11599 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits()); in LowerEXTRACT_VECTOR_ELT()
11600 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() / in LowerEXTRACT_VECTOR_ELT()
11601 MaskEltVT.getSizeInBits()); in LowerEXTRACT_VECTOR_ELT()
11624 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits(); in LowerEXTRACT_VECTOR_ELT()
11642 if (VT.getSizeInBits() == 16) { in LowerEXTRACT_VECTOR_ELT()
11658 if (VT.getSizeInBits() == 32) { in LowerEXTRACT_VECTOR_ELT()
11672 if (VT.getSizeInBits() == 64) { in LowerEXTRACT_VECTOR_ELT()
11762 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits(); in LowerINSERT_VECTOR_ELT()
11776 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) { in LowerINSERT_VECTOR_ELT()
11832 if (EltVT.getSizeInBits() == 16) { in LowerINSERT_VECTOR_ELT()
11852 unsigned SizeFactor = OpVT.getSizeInBits()/128; in LowerSCALAR_TO_VECTOR()
12462 unsigned VTBits = VT.getSizeInBits(); in LowerShiftParts()
12544 unsigned Size = SrcVT.getSizeInBits()/8; in LowerSINT_TO_FP()
12568 unsigned ByteSize = SrcVT.getSizeInBits()/8; in BuildFILD()
12594 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; in BuildFILD()
13027 unsigned MemSize = DstTy.getSizeInBits()/8; in FP_TO_INTHelper()
13268 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) && in LowerTRUNCATE()
13270 if (InVT.getSizeInBits() >= 32) in LowerTRUNCATE()
13300 if (InVT.getSizeInBits() < 512) { in LowerTRUNCATE()
13516 unsigned EltBits = EltVT.getSizeInBits(); in LowerFABSorFNEG()
13577 const unsigned SizeInBits = VT.getSizeInBits(); in LowerFCOPYSIGN()
13887 unsigned BitWidth = VT.getSizeInBits(); in EmitTest()
14323 assert(Op0.getSimpleValueType().getVectorElementType().getSizeInBits() >= 8 && in LowerIntVSETCC_AVX512()
14470 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32)) in LowerVSETCC()
14478 (OpVT.getVectorElementType().getSizeInBits() < 32 && in LowerVSETCC()
14479 OpVT.getVectorElementType().getSizeInBits() >= 8)) in LowerVSETCC()
14661 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl, in LowerVSETCC()
14889 if (newSelect.getValueSizeInBits() == VT.getSizeInBits()) in LowerSELECT()
15101 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) || in LowerSIGN_EXTEND_AVX512()
15104 VTElt.getSizeInBits() <= 16)) || in LowerSIGN_EXTEND_AVX512()
15107 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) || in LowerSIGN_EXTEND_AVX512()
15110 VTElt.getSizeInBits() >= 32)))) in LowerSIGN_EXTEND_AVX512()
15144 assert(VT.getSizeInBits() == InVT.getSizeInBits()); in LowerSIGN_EXTEND_VECTOR_INREG()
15147 assert(VT.getVectorElementType().getSizeInBits() > InSVT.getSizeInBits()); in LowerSIGN_EXTEND_VECTOR_INREG()
15176 CurrVT.getVectorElementType().getSizeInBits() - InSVT.getSizeInBits(); in LowerSIGN_EXTEND_VECTOR_INREG()
15266 unsigned RegSz = RegVT.getSizeInBits(); in LowerExtendedLoad()
15276 unsigned MemSz = MemVT.getSizeInBits(); in LowerExtendedLoad()
15330 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) { in LowerExtendedLoad()
15336 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 && in LowerExtendedLoad()
15342 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits(); in LowerExtendedLoad()
15354 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits()); in LowerExtendedLoad()
15362 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() && in LowerExtendedLoad()
15371 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl, in LowerExtendedLoad()
15982 if (ShiftAmt >= ElementType.getSizeInBits()) { in getTargetVShiftByConstNode()
15984 ShiftAmt = ElementType.getSizeInBits() - 1; in getTargetVShiftByConstNode()
16094 MVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits()); in getTargetVShiftNode()
16109 MVT::getIntegerVT(MaskVT.getSizeInBits()), Mask); in getMaskNode()
16129 MVT TruncVT = MVT::getIntegerVT(MaskVT.getSizeInBits()); in getMaskNode()
16136 Mask.getSimpleValueType().getSizeInBits()); in getMaskNode()
16571 Mask.getSimpleValueType().getSizeInBits()); in LowerINTRINSIC_WO_CHAIN()
16605 Mask.getSimpleValueType().getSizeInBits()); in LowerINTRINSIC_WO_CHAIN()
16717 MVT MaskVT = MVT::getVectorVT(MVT::i1, Mask.getSimpleValueType().getSizeInBits()); in LowerINTRINSIC_WO_CHAIN()
16731 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getSizeInBits()/2); in LowerINTRINSIC_WO_CHAIN()
16737 MVT::getVectorVT(MVT::i1, VT.getSizeInBits()), in LowerINTRINSIC_WO_CHAIN()
16964 Mask.getSimpleValueType().getSizeInBits()); in getGatherNode()
16999 Mask.getSimpleValueType().getSizeInBits()); in getScatterNode()
17182 Mask.getSimpleValueType().getSizeInBits()); in LowerINTRINSIC_TRUNCATE_TO_MEM()
17744 return DAG.getNode((VT.getSizeInBits() < 16 ? in LowerFLT_ROUNDS_()
17802 SDValue Delta = DAG.getConstant(32 - EltVT.getSizeInBits(), dl, VT); in LowerVectorCTLZ_AVX512()
17811 unsigned NumBits = VT.getSizeInBits(); in LowerCTLZ()
17850 unsigned NumBits = VT.getSizeInBits(); in LowerCTLZ_ZERO_UNDEF()
18135 assert(VT.isInteger() && VT.getSizeInBits() == 128 && in LowerWin64_i128OP()
18157 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 && in LowerWin64_i128OP()
18625 unsigned SVTBits = SVT.getSizeInBits(); in LowerShift()
19373 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && in LowerBITCAST()
19404 unsigned VecSize = VT.getSizeInBits(); in LowerHorizontalByteSum()
19405 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!"); in LowerHorizontalByteSum()
19463 unsigned VecSize = VT.getSizeInBits(); in LowerVectorCTPOPInRegLUT()
19525 int VecSize = VT.getSizeInBits(); in LowerVectorCTPOPBitmath()
19527 int Len = EltVT.getSizeInBits(); in LowerVectorCTPOPBitmath()
20172 auto InVTSize = InVT.getSizeInBits(); in ReplaceNodeResults()
20182 RegSize / ElemVT.getSizeInBits()); in ReplaceNodeResults()
20183 assert(RegSize % InVT.getSizeInBits() == 0); in ReplaceNodeResults()
20184 unsigned NumConcat = RegSize / InVT.getSizeInBits(); in ReplaceNodeResults()
20753 unsigned NumBits1 = VT1.getSizeInBits(); in isTruncateFree()
20754 unsigned NumBits2 = VT2.getSizeInBits(); in isTruncateFree()
20835 if (VT.getSimpleVT().getSizeInBits() == 64) in isShuffleMaskLegal()
22901 int NumBytes = VT.getSizeInBits() / 8; in combineX86ShuffleChain()
22980 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() && in combineX86ShufflesRecursively()
23090 if (VT.getSizeInBits() > 128) { in getPSHUFShuffleMask()
23093 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i) in getPSHUFShuffleMask()
23881 unsigned EltSize = ElementType.getSizeInBits() / 8; in PerformEXTRACT_VECTOR_ELTCombine()
25013 unsigned Size = VT.getSizeInBits(); in PerformSRACombine()
25041 unsigned ShiftSize = SVT.getSizeInBits(); in PerformSRACombine()
25080 VT.getSimpleVT().getVectorElementType().getSizeInBits(); in performShiftToAllZeros()
25487 if (Shift + MaskSize <= VT.getSizeInBits()) in PerformAndCombine()
25573 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); in PerformOrCombine()
25655 unsigned Bits = VT.getSizeInBits(); in PerformOrCombine()
25687 if (VT.isInteger() && VT.getSizeInBits() == 8) in performIntegerAbsCombine()
25702 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) { in performIntegerAbsCombine()
25747 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1) in foldXorTruncShiftIntoCmp()
25798 if (InScalarVT.getSizeInBits() <= ScalarVT.getSizeInBits()) in detectAVGPattern()
25802 if (VT.getSizeInBits() > 512) in detectAVGPattern()
25805 if (VT.getSizeInBits() > 256) in detectAVGPattern()
25808 if (VT.getSizeInBits() > 128) in detectAVGPattern()
25966 unsigned ToSz = VT.getVectorElementType().getSizeInBits(); in PerformMLOADCombine()
25967 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits(); in PerformMLOADCombine()
25973 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits()); in PerformMLOADCombine()
25978 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); in PerformMLOADCombine()
26045 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); in PerformMSTORECombine()
26046 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); in PerformMSTORECombine()
26066 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); in PerformMSTORECombine()
26072 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); in PerformMSTORECombine()
26178 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); in PerformSTORECombine()
26179 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); in PerformSTORECombine()
26196 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); in PerformSTORECombine()
26202 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); in PerformSTORECombine()
26222 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz) in PerformSTORECombine()
26227 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 && in PerformSTORECombine()
26233 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits()); in PerformSTORECombine()
26234 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); in PerformSTORECombine()
26237 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl, in PerformSTORECombine()
26242 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) { in PerformSTORECombine()
26262 if (VT.getSizeInBits() != 64) in PerformSTORECombine()
26425 unsigned NumLanes = VT.getSizeInBits()/128; in isHorizontalBinOp()
26577 for (unsigned j = 1, e = InSVT.getSizeInBits() / OutSVT.getSizeInBits(); in combineVectorTruncationWithPACKUS()
26666 unsigned RegNum = InVT.getSizeInBits() / 128; in combineVectorTruncation()
26914 VT.getVectorElementType().getSizeInBits() == in PerformVZEXT_MOVLCombine()
26915 OpVT.getVectorElementType().getSizeInBits()) { in PerformVZEXT_MOVLCombine()
26947 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) { in PerformSIGN_EXTEND_INREGCombine()
27034 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT); in PerformSExtCombine()
27045 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(), in PerformSExtCombine()
27053 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) && in PerformSExtCombine()
27056 unsigned Scale = 128 / VT.getSizeInBits(); in PerformSExtCombine()
27058 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits()); in PerformSExtCombine()
27059 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits()); in PerformSExtCombine()
27067 if (VT.getSizeInBits() == 128 && in PerformSExtCombine()
27076 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) && in PerformSExtCombine()
27079 unsigned NumVecs = VT.getSizeInBits() / 128; in PerformSExtCombine()
27080 unsigned NumSubElts = 128 / SVT.getSizeInBits(); in PerformSExtCombine()
27399 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits()) in performVectorCompareAndMaskUnaryOpCombine()
27624 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements(); in performVZEXTCombine()
27644 if (InnerEltVT.getSizeInBits() < InputBits) in performVZEXTCombine()
27658 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) { in performVZEXTCombine()
27664 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) { in performVZEXTCombine()
27665 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits(); in performVZEXTCombine()
28462 unsigned Size = VT.getSizeInBits(); in getRegForInlineAsmConstraint()