Lines Matching refs:fmask
263 struct radeon_surface fmask = rtex->surface; in r600_texture_get_fmask_info() local
271 fmask.bpe = 4; in r600_texture_get_fmask_info()
272 fmask.nsamples = 2; in r600_texture_get_fmask_info()
275 fmask.bpe = 8; in r600_texture_get_fmask_info()
276 fmask.nsamples = 4; in r600_texture_get_fmask_info()
279 fmask.bpe = 16; in r600_texture_get_fmask_info()
280 fmask.nsamples = 4; in r600_texture_get_fmask_info()
289 fmask.bpe *= 2; in r600_texture_get_fmask_info()
293 fmask.bankh = nr_samples <= 4 ? 4 : 1; in r600_texture_get_fmask_info()
296 if (rscreen->ws->surface_init(rscreen->ws, &fmask)) { in r600_texture_get_fmask_info()
300 assert(fmask.level[0].mode == RADEON_SURF_MODE_2D); in r600_texture_get_fmask_info()
302 out->bank_height = fmask.bankh; in r600_texture_get_fmask_info()
303 out->alignment = MAX2(256, fmask.bo_alignment); in r600_texture_get_fmask_info()
304 out->size = (fmask.bo_size + 7) / 8; in r600_texture_get_fmask_info()
310 struct r600_fmask_info fmask; in r600_texture_allocate_fmask() local
313 rtex->resource.b.b.nr_samples, &fmask); in r600_texture_allocate_fmask()
316 rtex->fmask_bank_height = fmask.bank_height; in r600_texture_allocate_fmask()
317 rtex->fmask_offset = align(rtex->size, fmask.alignment); in r600_texture_allocate_fmask()
318 rtex->fmask_size = fmask.size; in r600_texture_allocate_fmask()
322 fmask.npix_x, fmask.npix_y, fmask.bpe * fmask.nsamples, rtex->fmask_size); in r600_texture_allocate_fmask()