38                                            unsigned &SubIdx) const {  in isCoalescableExtInstr()
44                                              int &FrameIndex) const {  in isLoadFromStackSlot()
50                                                    int &FrameIndex) const {  in isLoadFromStackSlotPostFE()
57                                           int &FrameIndex) const {  in hasLoadFromStackSlot()
62                                               int &FrameIndex) const {  in isStoreFromStackSlot()
67                                                     int &FrameIndex) const {  in isStoreFromStackSlotPostFE()
73                                            int &FrameIndex) const {  in hasStoreFromStackSlot()
81                                       LiveVariables *LV) const {  in convertToThreeAddress()
86                                         MachineBasicBlock &MBB) const {  in getNextBranchInstr()
127                                     const TargetRegisterInfo *TRI) const {  in storeRegToStackSlot()  argument
136                                      const TargetRegisterInfo *TRI) const {  in loadRegFromStackSlot()  argument
144                                       int FrameIndex) const {  in foldMemoryOperandImpl()
152                                       MachineInstr *LoadMI) const {  in foldMemoryOperandImpl()
158                                      const SmallVectorImpl<unsigned> &Ops) const  in canFoldMemoryOperand()  argument
167                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {  in unfoldMemoryOperand()
174                                     SmallVectorImpl<SDNode*> &NewNodes) const {  in unfoldMemoryOperand()
182                                            unsigned *LoadRegIndex) const {  in getOpcodeAfterMemoryUnfold()
189                                              unsigned NumLoads) const {  in shouldScheduleLoadsNear()
199 AMDGPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)  in ReverseBranchCondition()
205                                 MachineBasicBlock::iterator MI) const {  in insertNoop()
209 bool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const {  in isPredicated()  argument
215                                   const SmallVectorImpl<MachineOperand> &Pred2)  in SubsumesPredicate()
222                                       std::vector<MachineOperand> &Pred) const {  in DefinesPredicate()
227 bool AMDGPUInstrInfo::isPredicable(MachineInstr *MI) const {  in isPredicable()
233 AMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {  in isSafeToMoveRegClassDefs()  argument
239     DebugLoc DL) const  in convertToISA()