Lines Matching refs:rn
1092 const Register& rn, in add() argument
1094 AddSub(rd, rn, operand, LeaveFlags, ADD); in add()
1099 const Register& rn, in adds() argument
1101 AddSub(rd, rn, operand, SetFlags, ADD); in adds()
1105 void Assembler::cmn(const Register& rn, in cmn() argument
1107 Register zr = AppropriateZeroRegFor(rn); in cmn()
1108 adds(zr, rn, operand); in cmn()
1113 const Register& rn, in sub() argument
1115 AddSub(rd, rn, operand, LeaveFlags, SUB); in sub()
1120 const Register& rn, in subs() argument
1122 AddSub(rd, rn, operand, SetFlags, SUB); in subs()
1126 void Assembler::cmp(const Register& rn, const Operand& operand) { in cmp() argument
1127 Register zr = AppropriateZeroRegFor(rn); in cmp()
1128 subs(zr, rn, operand); in cmp()
1145 const Register& rn, in adc() argument
1147 AddSubWithCarry(rd, rn, operand, LeaveFlags, ADC); in adc()
1152 const Register& rn, in adcs() argument
1154 AddSubWithCarry(rd, rn, operand, SetFlags, ADC); in adcs()
1159 const Register& rn, in sbc() argument
1161 AddSubWithCarry(rd, rn, operand, LeaveFlags, SBC); in sbc()
1166 const Register& rn, in sbcs() argument
1168 AddSubWithCarry(rd, rn, operand, SetFlags, SBC); in sbcs()
1186 const Register& rn, in and_() argument
1188 Logical(rd, rn, operand, AND); in and_()
1193 const Register& rn, in ands() argument
1195 Logical(rd, rn, operand, ANDS); in ands()
1199 void Assembler::tst(const Register& rn, in tst() argument
1201 ands(AppropriateZeroRegFor(rn), rn, operand); in tst()
1206 const Register& rn, in bic() argument
1208 Logical(rd, rn, operand, BIC); in bic()
1213 const Register& rn, in bics() argument
1215 Logical(rd, rn, operand, BICS); in bics()
1220 const Register& rn, in orr() argument
1222 Logical(rd, rn, operand, ORR); in orr()
1227 const Register& rn, in orn() argument
1229 Logical(rd, rn, operand, ORN); in orn()
1234 const Register& rn, in eor() argument
1236 Logical(rd, rn, operand, EOR); in eor()
1241 const Register& rn, in eon() argument
1243 Logical(rd, rn, operand, EON); in eon()
1248 const Register& rn, in lslv() argument
1250 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in lslv()
1252 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd)); in lslv()
1257 const Register& rn, in lsrv() argument
1259 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in lsrv()
1261 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd)); in lsrv()
1266 const Register& rn, in asrv() argument
1268 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in asrv()
1270 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd)); in asrv()
1275 const Register& rn, in rorv() argument
1277 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in rorv()
1279 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd)); in rorv()
1284 void Assembler::bfm(const Register& rd, const Register& rn, int immr, in bfm() argument
1286 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in bfm()
1290 ImmS(imms, rn.SizeInBits()) | in bfm()
1291 Rn(rn) | Rd(rd)); in bfm()
1295 void Assembler::sbfm(const Register& rd, const Register& rn, int immr, in sbfm() argument
1297 DCHECK(rd.Is64Bits() || rn.Is32Bits()); in sbfm()
1301 ImmS(imms, rn.SizeInBits()) | in sbfm()
1302 Rn(rn) | Rd(rd)); in sbfm()
1306 void Assembler::ubfm(const Register& rd, const Register& rn, int immr, in ubfm() argument
1308 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in ubfm()
1312 ImmS(imms, rn.SizeInBits()) | in ubfm()
1313 Rn(rn) | Rd(rd)); in ubfm()
1317 void Assembler::extr(const Register& rd, const Register& rn, const Register& rm, in extr() argument
1319 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in extr()
1323 ImmS(lsb, rn.SizeInBits()) | Rn(rn) | Rd(rd)); in extr()
1328 const Register& rn, in csel() argument
1331 ConditionalSelect(rd, rn, rm, cond, CSEL); in csel()
1336 const Register& rn, in csinc() argument
1339 ConditionalSelect(rd, rn, rm, cond, CSINC); in csinc()
1344 const Register& rn, in csinv() argument
1347 ConditionalSelect(rd, rn, rm, cond, CSINV); in csinv()
1352 const Register& rn, in csneg() argument
1355 ConditionalSelect(rd, rn, rm, cond, CSNEG); in csneg()
1373 void Assembler::cinc(const Register &rd, const Register &rn, Condition cond) { in cinc() argument
1375 csinc(rd, rn, rn, NegateCondition(cond)); in cinc()
1379 void Assembler::cinv(const Register &rd, const Register &rn, Condition cond) { in cinv() argument
1381 csinv(rd, rn, rn, NegateCondition(cond)); in cinv()
1385 void Assembler::cneg(const Register &rd, const Register &rn, Condition cond) { in cneg() argument
1387 csneg(rd, rn, rn, NegateCondition(cond)); in cneg()
1392 const Register& rn, in ConditionalSelect() argument
1396 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in ConditionalSelect()
1398 Emit(SF(rd) | op | Rm(rm) | Cond(cond) | Rn(rn) | Rd(rd)); in ConditionalSelect()
1402 void Assembler::ccmn(const Register& rn, in ccmn() argument
1406 ConditionalCompare(rn, operand, nzcv, cond, CCMN); in ccmn()
1410 void Assembler::ccmp(const Register& rn, in ccmp() argument
1414 ConditionalCompare(rn, operand, nzcv, cond, CCMP); in ccmp()
1419 const Register& rn, in DataProcessing3Source() argument
1423 Emit(SF(rd) | op | Rm(rm) | Ra(ra) | Rn(rn) | Rd(rd)); in DataProcessing3Source()
1428 const Register& rn, in mul() argument
1430 DCHECK(AreSameSizeAndType(rd, rn, rm)); in mul()
1431 Register zr = AppropriateZeroRegFor(rn); in mul()
1432 DataProcessing3Source(rd, rn, rm, zr, MADD); in mul()
1437 const Register& rn, in madd() argument
1440 DCHECK(AreSameSizeAndType(rd, rn, rm, ra)); in madd()
1441 DataProcessing3Source(rd, rn, rm, ra, MADD); in madd()
1446 const Register& rn, in mneg() argument
1448 DCHECK(AreSameSizeAndType(rd, rn, rm)); in mneg()
1449 Register zr = AppropriateZeroRegFor(rn); in mneg()
1450 DataProcessing3Source(rd, rn, rm, zr, MSUB); in mneg()
1455 const Register& rn, in msub() argument
1458 DCHECK(AreSameSizeAndType(rd, rn, rm, ra)); in msub()
1459 DataProcessing3Source(rd, rn, rm, ra, MSUB); in msub()
1464 const Register& rn, in smaddl() argument
1468 DCHECK(rn.Is32Bits() && rm.Is32Bits()); in smaddl()
1469 DataProcessing3Source(rd, rn, rm, ra, SMADDL_x); in smaddl()
1474 const Register& rn, in smsubl() argument
1478 DCHECK(rn.Is32Bits() && rm.Is32Bits()); in smsubl()
1479 DataProcessing3Source(rd, rn, rm, ra, SMSUBL_x); in smsubl()
1484 const Register& rn, in umaddl() argument
1488 DCHECK(rn.Is32Bits() && rm.Is32Bits()); in umaddl()
1489 DataProcessing3Source(rd, rn, rm, ra, UMADDL_x); in umaddl()
1494 const Register& rn, in umsubl() argument
1498 DCHECK(rn.Is32Bits() && rm.Is32Bits()); in umsubl()
1499 DataProcessing3Source(rd, rn, rm, ra, UMSUBL_x); in umsubl()
1504 const Register& rn, in smull() argument
1507 DCHECK(rn.Is32Bits() && rm.Is32Bits()); in smull()
1508 DataProcessing3Source(rd, rn, rm, xzr, SMADDL_x); in smull()
1513 const Register& rn, in smulh() argument
1515 DCHECK(AreSameSizeAndType(rd, rn, rm)); in smulh()
1516 DataProcessing3Source(rd, rn, rm, xzr, SMULH_x); in smulh()
1521 const Register& rn, in sdiv() argument
1523 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in sdiv()
1525 Emit(SF(rd) | SDIV | Rm(rm) | Rn(rn) | Rd(rd)); in sdiv()
1530 const Register& rn, in udiv() argument
1532 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in udiv()
1534 Emit(SF(rd) | UDIV | Rm(rm) | Rn(rn) | Rd(rd)); in udiv()
1539 const Register& rn) { in rbit() argument
1540 DataProcessing1Source(rd, rn, RBIT); in rbit()
1545 const Register& rn) { in rev16() argument
1546 DataProcessing1Source(rd, rn, REV16); in rev16()
1551 const Register& rn) { in rev32() argument
1553 DataProcessing1Source(rd, rn, REV); in rev32()
1558 const Register& rn) { in rev() argument
1559 DataProcessing1Source(rd, rn, rd.Is64Bits() ? REV_x : REV_w); in rev()
1564 const Register& rn) { in clz() argument
1565 DataProcessing1Source(rd, rn, CLZ); in clz()
1570 const Register& rn) { in cls() argument
1571 DataProcessing1Source(rd, rn, CLS); in cls()
1766 void Assembler::fmov(FPRegister fd, Register rn) { in fmov() argument
1767 DCHECK(fd.SizeInBits() == rn.SizeInBits()); in fmov()
1769 Emit(op | Rd(fd) | Rn(rn)); in fmov()
2021 const Register& rn, in scvtf() argument
2024 Emit(SF(rn) | FPType(fd) | SCVTF | Rn(rn) | Rd(fd)); in scvtf()
2026 Emit(SF(rn) | FPType(fd) | SCVTF_fixed | FPScale(64 - fbits) | Rn(rn) | in scvtf()
2033 const Register& rn, in ucvtf() argument
2036 Emit(SF(rn) | FPType(fd) | UCVTF | Rn(rn) | Rd(fd)); in ucvtf()
2038 Emit(SF(rn) | FPType(fd) | UCVTF_fixed | FPScale(64 - fbits) | Rn(rn) | in ucvtf()
2170 const Register& rn, in AddSub() argument
2174 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in AddSub()
2181 ImmAddSub(static_cast<int>(immediate)) | dest_reg | RnSP(rn)); in AddSub()
2193 if (rn.IsSP() || rd.IsSP()) { in AddSub()
2195 DataProcExtendedRegister(rd, rn, operand.ToExtendedRegister(), S, in AddSub()
2198 DataProcShiftedRegister(rd, rn, operand, S, AddSubShiftedFixed | op); in AddSub()
2202 DataProcExtendedRegister(rd, rn, operand, S, AddSubExtendedFixed | op); in AddSub()
2208 const Register& rn, in AddSubWithCarry() argument
2212 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in AddSubWithCarry()
2216 Emit(SF(rd) | op | Flags(S) | Rm(operand.reg()) | Rn(rn) | Rd(rd)); in AddSubWithCarry()
2278 const Register& rn, in Logical() argument
2281 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in Logical()
2300 LogicalImmediate(rd, rn, n, imm_s, imm_r, op); in Logical()
2309 DataProcShiftedRegister(rd, rn, operand, LeaveFlags, dp_op); in Logical()
2315 const Register& rn, in LogicalImmediate() argument
2324 Rn(rn)); in LogicalImmediate()
2328 void Assembler::ConditionalCompare(const Register& rn, in ConditionalCompare() argument
2344 Emit(SF(rn) | ccmpop | Cond(cond) | Rn(rn) | Nzcv(nzcv)); in ConditionalCompare()
2349 const Register& rn, in DataProcessing1Source() argument
2351 DCHECK(rd.SizeInBits() == rn.SizeInBits()); in DataProcessing1Source()
2352 Emit(SF(rn) | op | Rn(rn) | Rd(rd)); in DataProcessing1Source()
2384 const Register& rn, in EmitShift() argument
2389 lsl(rd, rn, shift_amount); in EmitShift()
2392 lsr(rd, rn, shift_amount); in EmitShift()
2395 asr(rd, rn, shift_amount); in EmitShift()
2398 ror(rd, rn, shift_amount); in EmitShift()
2407 const Register& rn, in EmitExtendShift() argument
2410 DCHECK(rd.SizeInBits() >= rn.SizeInBits()); in EmitExtendShift()
2413 Register rn_ = Register::Create(rn.code(), rd.SizeInBits()); in EmitExtendShift()
2429 DCHECK(rn.SizeInBits() == kXRegSizeInBits); in EmitExtendShift()
2444 const Register& rn, in DataProcShiftedRegister() argument
2449 DCHECK(rn.Is64Bits() || (rn.Is32Bits() && is_uint5(operand.shift_amount()))); in DataProcShiftedRegister()
2453 Rm(operand.reg()) | Rn(rn) | Rd(rd)); in DataProcShiftedRegister()
2458 const Register& rn, in DataProcExtendedRegister() argument
2466 dest_reg | RnSP(rn)); in DataProcExtendedRegister()