94 static cache_t2 I1, D1, LL;  variable
319     if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit;  in cachesim_I1_ref()
327     if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit;  in cachesim_D1_ref()
427     switch( cachesim_ref_wb( &LL, Read, a, size) ) {  in cachesim_I1_Read()
439     switch( cachesim_ref_wb( &LL, Read, a, size) ) {  in cachesim_D1_Read()
455 	cachesim_ref_wb( &LL, Write, a, size);  in cachesim_D1_Write()
458     switch( cachesim_ref_wb( &LL, Write, a, size) ) {  in cachesim_D1_Write()
497   UInt block = ( a >> LL.line_size_bits);  in prefetch_LL_doref()
509 	  cachesim_ref(&LL, a + 5 * LL.line_size,1);  in prefetch_LL_doref()
519 	  cachesim_ref(&LL, a - 5 * LL.line_size,1);  in prefetch_LL_doref()
535     if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit;  in prefetch_I1_ref()
544     if ( cachesim_ref( &LL, a, size) == Hit ) return LL_Hit;  in prefetch_D1_ref()
556     switch( cachesim_ref_wb( &LL, Read, a, size) ) {  in prefetch_I1_Read()
569     switch( cachesim_ref_wb( &LL, Read, a, size) ) {  in prefetch_D1_Read()
586 	cachesim_ref_wb( &LL, Write, a, size);  in prefetch_D1_Write()
589     switch( cachesim_ref_wb( &LL, Write, a, size) ) {  in prefetch_D1_Write()
854   line_loaded* loaded = &(LL.loaded[idx]);  in update_LL_use()
855   line_use* use = &(LL.use[idx]);  in update_LL_use()
856   int i = ((32 - countBits(use->mask)) * LL.line_size)>>5;  in update_LL_use()
885    UInt setNo = (memline >> LL.line_size_bits) & (LL.sets_min_1);  in cacheuse_LL_access()
886    UWord* set = &(LL.tags[setNo * LL.assoc]);  in cacheuse_LL_access()
887    UWord tag  = memline & LL.tag_mask;  in cacheuse_LL_access()
894    if (tag == (set[0] & LL.tag_mask)) {  in cacheuse_LL_access()
895      idx = (setNo * LL.assoc) + (set[0] & ~LL.tag_mask);  in cacheuse_LL_access()
896      l1_loaded->dep_use = &(LL.use[idx]);  in cacheuse_LL_access()
899 		 idx, LL.loaded[idx].memline,  LL.loaded[idx].iaddr,  in cacheuse_LL_access()
900 		 LL.use[idx].mask, LL.use[idx].count);  in cacheuse_LL_access()
903    for (i = 1; i < LL.assoc; i++) {  in cacheuse_LL_access()
904      if (tag == (set[i] & LL.tag_mask)) {  in cacheuse_LL_access()
910        idx = (setNo * LL.assoc) + (tmp_tag & ~LL.tag_mask);  in cacheuse_LL_access()
911        l1_loaded->dep_use = &(LL.use[idx]);  in cacheuse_LL_access()
914 		 i, idx, LL.loaded[idx].memline,  LL.loaded[idx].iaddr,  in cacheuse_LL_access()
915 		 LL.use[idx].mask, LL.use[idx].count);  in cacheuse_LL_access()
921    tmp_tag = set[LL.assoc - 1] & ~LL.tag_mask;  in cacheuse_LL_access()
922    for (j = LL.assoc - 1; j > 0; j--) {  in cacheuse_LL_access()
926    idx = (setNo * LL.assoc) + tmp_tag;  in cacheuse_LL_access()
927    l1_loaded->dep_use = &(LL.use[idx]);  in cacheuse_LL_access()
1006   if (LL.use)  in cacheuse_finish()
1007     for (i = 0; i < LL.sets * LL.assoc; i++)  in cacheuse_finish()
1008       if (LL.loaded[i].use_base)  in cacheuse_finish()
1324   LL.name = "LL";  in cachesim_post_clo_init()
1350   cachesim_initcache(LLc, &LL);  in cachesim_post_clo_init()
1431   cachesim_clearcache(&LL);  in cachesim_clear()
1441   VG_(fprintf)(fp, "desc: LL cache: %s\n", LL.desc_line);  in cachesim_dump_desc()