1 /* 2 * Copyright (c) 2015 The WebM project authors. All Rights Reserved. 3 * 4 * Use of this source code is governed by a BSD-style license 5 * that can be found in the LICENSE file in the root of the source 6 * tree. An additional intellectual property rights grant can be found 7 * in the file PATENTS. All contributing project authors may 8 * be found in the AUTHORS file in the root of the source tree. 9 */ 10 11 #ifndef VPX_DSP_MIPS_TXFM_MACROS_MIPS_MSA_H_ 12 #define VPX_DSP_MIPS_TXFM_MACROS_MIPS_MSA_H_ 13 14 #include "vpx_dsp/mips/macros_msa.h" 15 16 #define DOTP_CONST_PAIR(reg0, reg1, cnst0, cnst1, out0, out1) { \ 17 v8i16 k0_m = __msa_fill_h(cnst0); \ 18 v4i32 s0_m, s1_m, s2_m, s3_m; \ 19 \ 20 s0_m = (v4i32)__msa_fill_h(cnst1); \ 21 k0_m = __msa_ilvev_h((v8i16)s0_m, k0_m); \ 22 \ 23 ILVRL_H2_SW((-reg1), reg0, s1_m, s0_m); \ 24 ILVRL_H2_SW(reg0, reg1, s3_m, s2_m); \ 25 DOTP_SH2_SW(s1_m, s0_m, k0_m, k0_m, s1_m, s0_m); \ 26 SRARI_W2_SW(s1_m, s0_m, DCT_CONST_BITS); \ 27 out0 = __msa_pckev_h((v8i16)s0_m, (v8i16)s1_m); \ 28 \ 29 DOTP_SH2_SW(s3_m, s2_m, k0_m, k0_m, s1_m, s0_m); \ 30 SRARI_W2_SW(s1_m, s0_m, DCT_CONST_BITS); \ 31 out1 = __msa_pckev_h((v8i16)s0_m, (v8i16)s1_m); \ 32 } 33 34 #define DOT_ADD_SUB_SRARI_PCK(in0, in1, in2, in3, in4, in5, in6, in7, \ 35 dst0, dst1, dst2, dst3) { \ 36 v4i32 tp0_m, tp1_m, tp2_m, tp3_m, tp4_m; \ 37 v4i32 tp5_m, tp6_m, tp7_m, tp8_m, tp9_m; \ 38 \ 39 DOTP_SH4_SW(in0, in1, in0, in1, in4, in4, in5, in5, \ 40 tp0_m, tp2_m, tp3_m, tp4_m); \ 41 DOTP_SH4_SW(in2, in3, in2, in3, in6, in6, in7, in7, \ 42 tp5_m, tp6_m, tp7_m, tp8_m); \ 43 BUTTERFLY_4(tp0_m, tp3_m, tp7_m, tp5_m, tp1_m, tp9_m, tp7_m, tp5_m); \ 44 BUTTERFLY_4(tp2_m, tp4_m, tp8_m, tp6_m, tp3_m, tp0_m, tp4_m, tp2_m); \ 45 SRARI_W4_SW(tp1_m, tp9_m, tp7_m, tp5_m, DCT_CONST_BITS); \ 46 SRARI_W4_SW(tp3_m, tp0_m, tp4_m, tp2_m, DCT_CONST_BITS); \ 47 PCKEV_H4_SH(tp1_m, tp3_m, tp9_m, tp0_m, tp7_m, tp4_m, tp5_m, tp2_m, \ 48 dst0, dst1, dst2, dst3); \ 49 } 50 51 #define DOT_SHIFT_RIGHT_PCK_H(in0, in1, in2) ({ \ 52 v8i16 dst_m; \ 53 v4i32 tp0_m, tp1_m; \ 54 \ 55 DOTP_SH2_SW(in0, in1, in2, in2, tp1_m, tp0_m); \ 56 SRARI_W2_SW(tp1_m, tp0_m, DCT_CONST_BITS); \ 57 dst_m = __msa_pckev_h((v8i16)tp1_m, (v8i16)tp0_m); \ 58 \ 59 dst_m; \ 60 }) 61 62 #define MADD_SHORT(m0, m1, c0, c1, res0, res1) { \ 63 v4i32 madd0_m, madd1_m, madd2_m, madd3_m; \ 64 v8i16 madd_s0_m, madd_s1_m; \ 65 \ 66 ILVRL_H2_SH(m1, m0, madd_s0_m, madd_s1_m); \ 67 DOTP_SH4_SW(madd_s0_m, madd_s1_m, madd_s0_m, madd_s1_m, \ 68 c0, c0, c1, c1, madd0_m, madd1_m, madd2_m, madd3_m); \ 69 SRARI_W4_SW(madd0_m, madd1_m, madd2_m, madd3_m, DCT_CONST_BITS); \ 70 PCKEV_H2_SH(madd1_m, madd0_m, madd3_m, madd2_m, res0, res1); \ 71 } 72 73 #define MADD_BF(inp0, inp1, inp2, inp3, cst0, cst1, cst2, cst3, \ 74 out0, out1, out2, out3) { \ 75 v8i16 madd_s0_m, madd_s1_m, madd_s2_m, madd_s3_m; \ 76 v4i32 tmp0_m, tmp1_m, tmp2_m, tmp3_m, m4_m, m5_m; \ 77 \ 78 ILVRL_H2_SH(inp1, inp0, madd_s0_m, madd_s1_m); \ 79 ILVRL_H2_SH(inp3, inp2, madd_s2_m, madd_s3_m); \ 80 DOTP_SH4_SW(madd_s0_m, madd_s1_m, madd_s2_m, madd_s3_m, \ 81 cst0, cst0, cst2, cst2, tmp0_m, tmp1_m, tmp2_m, tmp3_m); \ 82 BUTTERFLY_4(tmp0_m, tmp1_m, tmp3_m, tmp2_m, \ 83 m4_m, m5_m, tmp3_m, tmp2_m); \ 84 SRARI_W4_SW(m4_m, m5_m, tmp2_m, tmp3_m, DCT_CONST_BITS); \ 85 PCKEV_H2_SH(m5_m, m4_m, tmp3_m, tmp2_m, out0, out1); \ 86 DOTP_SH4_SW(madd_s0_m, madd_s1_m, madd_s2_m, madd_s3_m, \ 87 cst1, cst1, cst3, cst3, tmp0_m, tmp1_m, tmp2_m, tmp3_m); \ 88 BUTTERFLY_4(tmp0_m, tmp1_m, tmp3_m, tmp2_m, \ 89 m4_m, m5_m, tmp3_m, tmp2_m); \ 90 SRARI_W4_SW(m4_m, m5_m, tmp2_m, tmp3_m, DCT_CONST_BITS); \ 91 PCKEV_H2_SH(m5_m, m4_m, tmp3_m, tmp2_m, out2, out3); \ 92 } 93 #endif // VPX_DSP_MIPS_TXFM_MACROS_MIPS_MSA_H_ 94