1 //===-- MSP430InstrInfo.cpp - MSP430 Instruction Information --------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MSP430 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "MSP430InstrInfo.h"
15 #include "MSP430.h"
16 #include "MSP430MachineFunctionInfo.h"
17 #include "MSP430TargetMachine.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/IR/Function.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/TargetRegistry.h"
24
25 using namespace llvm;
26
27 #define GET_INSTRINFO_CTOR_DTOR
28 #include "MSP430GenInstrInfo.inc"
29
30 // Pin the vtable to this file.
anchor()31 void MSP430InstrInfo::anchor() {}
32
MSP430InstrInfo(MSP430Subtarget & STI)33 MSP430InstrInfo::MSP430InstrInfo(MSP430Subtarget &STI)
34 : MSP430GenInstrInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
35 RI() {}
36
storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,unsigned SrcReg,bool isKill,int FrameIdx,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const37 void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
38 MachineBasicBlock::iterator MI,
39 unsigned SrcReg, bool isKill, int FrameIdx,
40 const TargetRegisterClass *RC,
41 const TargetRegisterInfo *TRI) const {
42 DebugLoc DL;
43 if (MI != MBB.end()) DL = MI->getDebugLoc();
44 MachineFunction &MF = *MBB.getParent();
45 MachineFrameInfo &MFI = *MF.getFrameInfo();
46
47 MachineMemOperand *MMO = MF.getMachineMemOperand(
48 MachinePointerInfo::getFixedStack(MF, FrameIdx),
49 MachineMemOperand::MOStore, MFI.getObjectSize(FrameIdx),
50 MFI.getObjectAlignment(FrameIdx));
51
52 if (RC == &MSP430::GR16RegClass)
53 BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
54 .addFrameIndex(FrameIdx).addImm(0)
55 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
56 else if (RC == &MSP430::GR8RegClass)
57 BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
58 .addFrameIndex(FrameIdx).addImm(0)
59 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
60 else
61 llvm_unreachable("Cannot store this register to stack slot!");
62 }
63
loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,unsigned DestReg,int FrameIdx,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const64 void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
65 MachineBasicBlock::iterator MI,
66 unsigned DestReg, int FrameIdx,
67 const TargetRegisterClass *RC,
68 const TargetRegisterInfo *TRI) const{
69 DebugLoc DL;
70 if (MI != MBB.end()) DL = MI->getDebugLoc();
71 MachineFunction &MF = *MBB.getParent();
72 MachineFrameInfo &MFI = *MF.getFrameInfo();
73
74 MachineMemOperand *MMO = MF.getMachineMemOperand(
75 MachinePointerInfo::getFixedStack(MF, FrameIdx),
76 MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIdx),
77 MFI.getObjectAlignment(FrameIdx));
78
79 if (RC == &MSP430::GR16RegClass)
80 BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
81 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
82 else if (RC == &MSP430::GR8RegClass)
83 BuildMI(MBB, MI, DL, get(MSP430::MOV8rm))
84 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
85 else
86 llvm_unreachable("Cannot store this register to stack slot!");
87 }
88
copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,DebugLoc DL,unsigned DestReg,unsigned SrcReg,bool KillSrc) const89 void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
90 MachineBasicBlock::iterator I, DebugLoc DL,
91 unsigned DestReg, unsigned SrcReg,
92 bool KillSrc) const {
93 unsigned Opc;
94 if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
95 Opc = MSP430::MOV16rr;
96 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
97 Opc = MSP430::MOV8rr;
98 else
99 llvm_unreachable("Impossible reg-to-reg copy");
100
101 BuildMI(MBB, I, DL, get(Opc), DestReg)
102 .addReg(SrcReg, getKillRegState(KillSrc));
103 }
104
RemoveBranch(MachineBasicBlock & MBB) const105 unsigned MSP430InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
106 MachineBasicBlock::iterator I = MBB.end();
107 unsigned Count = 0;
108
109 while (I != MBB.begin()) {
110 --I;
111 if (I->isDebugValue())
112 continue;
113 if (I->getOpcode() != MSP430::JMP &&
114 I->getOpcode() != MSP430::JCC &&
115 I->getOpcode() != MSP430::Br &&
116 I->getOpcode() != MSP430::Bm)
117 break;
118 // Remove the branch.
119 I->eraseFromParent();
120 I = MBB.end();
121 ++Count;
122 }
123
124 return Count;
125 }
126
127 bool MSP430InstrInfo::
ReverseBranchCondition(SmallVectorImpl<MachineOperand> & Cond) const128 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
129 assert(Cond.size() == 1 && "Invalid Xbranch condition!");
130
131 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
132
133 switch (CC) {
134 default: llvm_unreachable("Invalid branch condition!");
135 case MSP430CC::COND_E:
136 CC = MSP430CC::COND_NE;
137 break;
138 case MSP430CC::COND_NE:
139 CC = MSP430CC::COND_E;
140 break;
141 case MSP430CC::COND_L:
142 CC = MSP430CC::COND_GE;
143 break;
144 case MSP430CC::COND_GE:
145 CC = MSP430CC::COND_L;
146 break;
147 case MSP430CC::COND_HS:
148 CC = MSP430CC::COND_LO;
149 break;
150 case MSP430CC::COND_LO:
151 CC = MSP430CC::COND_HS;
152 break;
153 }
154
155 Cond[0].setImm(CC);
156 return false;
157 }
158
isUnpredicatedTerminator(const MachineInstr * MI) const159 bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
160 if (!MI->isTerminator()) return false;
161
162 // Conditional branch is a special case.
163 if (MI->isBranch() && !MI->isBarrier())
164 return true;
165 if (!MI->isPredicable())
166 return true;
167 return !isPredicated(MI);
168 }
169
AnalyzeBranch(MachineBasicBlock & MBB,MachineBasicBlock * & TBB,MachineBasicBlock * & FBB,SmallVectorImpl<MachineOperand> & Cond,bool AllowModify) const170 bool MSP430InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
171 MachineBasicBlock *&TBB,
172 MachineBasicBlock *&FBB,
173 SmallVectorImpl<MachineOperand> &Cond,
174 bool AllowModify) const {
175 // Start from the bottom of the block and work up, examining the
176 // terminator instructions.
177 MachineBasicBlock::iterator I = MBB.end();
178 while (I != MBB.begin()) {
179 --I;
180 if (I->isDebugValue())
181 continue;
182
183 // Working from the bottom, when we see a non-terminator
184 // instruction, we're done.
185 if (!isUnpredicatedTerminator(I))
186 break;
187
188 // A terminator that isn't a branch can't easily be handled
189 // by this analysis.
190 if (!I->isBranch())
191 return true;
192
193 // Cannot handle indirect branches.
194 if (I->getOpcode() == MSP430::Br ||
195 I->getOpcode() == MSP430::Bm)
196 return true;
197
198 // Handle unconditional branches.
199 if (I->getOpcode() == MSP430::JMP) {
200 if (!AllowModify) {
201 TBB = I->getOperand(0).getMBB();
202 continue;
203 }
204
205 // If the block has any instructions after a JMP, delete them.
206 while (std::next(I) != MBB.end())
207 std::next(I)->eraseFromParent();
208 Cond.clear();
209 FBB = nullptr;
210
211 // Delete the JMP if it's equivalent to a fall-through.
212 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
213 TBB = nullptr;
214 I->eraseFromParent();
215 I = MBB.end();
216 continue;
217 }
218
219 // TBB is used to indicate the unconditinal destination.
220 TBB = I->getOperand(0).getMBB();
221 continue;
222 }
223
224 // Handle conditional branches.
225 assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch");
226 MSP430CC::CondCodes BranchCode =
227 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
228 if (BranchCode == MSP430CC::COND_INVALID)
229 return true; // Can't handle weird stuff.
230
231 // Working from the bottom, handle the first conditional branch.
232 if (Cond.empty()) {
233 FBB = TBB;
234 TBB = I->getOperand(0).getMBB();
235 Cond.push_back(MachineOperand::CreateImm(BranchCode));
236 continue;
237 }
238
239 // Handle subsequent conditional branches. Only handle the case where all
240 // conditional branches branch to the same destination.
241 assert(Cond.size() == 1);
242 assert(TBB);
243
244 // Only handle the case where all conditional branches branch to
245 // the same destination.
246 if (TBB != I->getOperand(0).getMBB())
247 return true;
248
249 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm();
250 // If the conditions are the same, we can leave them alone.
251 if (OldBranchCode == BranchCode)
252 continue;
253
254 return true;
255 }
256
257 return false;
258 }
259
260 unsigned
InsertBranch(MachineBasicBlock & MBB,MachineBasicBlock * TBB,MachineBasicBlock * FBB,ArrayRef<MachineOperand> Cond,DebugLoc DL) const261 MSP430InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
262 MachineBasicBlock *FBB,
263 ArrayRef<MachineOperand> Cond,
264 DebugLoc DL) const {
265 // Shouldn't be a fall through.
266 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
267 assert((Cond.size() == 1 || Cond.size() == 0) &&
268 "MSP430 branch conditions have one component!");
269
270 if (Cond.empty()) {
271 // Unconditional branch?
272 assert(!FBB && "Unconditional branch with multiple successors!");
273 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
274 return 1;
275 }
276
277 // Conditional branch.
278 unsigned Count = 0;
279 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
280 ++Count;
281
282 if (FBB) {
283 // Two-way Conditional branch. Insert the second branch.
284 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
285 ++Count;
286 }
287 return Count;
288 }
289
290 /// GetInstSize - Return the number of bytes of code the specified
291 /// instruction may be. This returns the maximum number of bytes.
292 ///
GetInstSizeInBytes(const MachineInstr * MI) const293 unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
294 const MCInstrDesc &Desc = MI->getDesc();
295
296 switch (Desc.TSFlags & MSP430II::SizeMask) {
297 default:
298 switch (Desc.getOpcode()) {
299 default: llvm_unreachable("Unknown instruction size!");
300 case TargetOpcode::CFI_INSTRUCTION:
301 case TargetOpcode::EH_LABEL:
302 case TargetOpcode::IMPLICIT_DEF:
303 case TargetOpcode::KILL:
304 case TargetOpcode::DBG_VALUE:
305 return 0;
306 case TargetOpcode::INLINEASM: {
307 const MachineFunction *MF = MI->getParent()->getParent();
308 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo();
309 return TII.getInlineAsmLength(MI->getOperand(0).getSymbolName(),
310 *MF->getTarget().getMCAsmInfo());
311 }
312 }
313 case MSP430II::SizeSpecial:
314 switch (MI->getOpcode()) {
315 default: llvm_unreachable("Unknown instruction size!");
316 case MSP430::SAR8r1c:
317 case MSP430::SAR16r1c:
318 return 4;
319 }
320 case MSP430II::Size2Bytes:
321 return 2;
322 case MSP430II::Size4Bytes:
323 return 4;
324 case MSP430II::Size6Bytes:
325 return 6;
326 }
327 }
328