Searched defs:Ord (Results 1 – 9 of 9) sorted by relevance
| /external/llvm/include/llvm/IR/ |
| D | Instructions.h | 57 inline bool isAtLeastAcquire(AtomicOrdering Ord) { in isAtLeastAcquire()
65 inline bool isAtLeastRelease(AtomicOrdering Ord) { in isAtLeastRelease()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64A57FPLoadBalancing.cpp | 529 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister() local
|
| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 1049 AtomicOrdering Ord) const { in emitLoadLinked()
1056 Value *Addr, AtomicOrdering Ord) const { in emitStoreConditional()
1091 AtomicOrdering Ord, bool IsStore, in emitLeadingFence()
1103 AtomicOrdering Ord, bool IsStore, in emitTrailingFence()
|
| /external/llvm/bindings/ocaml/llvm/ |
| D | llvm.ml | 137 | Ord Constructor
|
| D | llvm.mli | 194 | Ord (** Ordered (no operand is NaN) *) Constructor
|
| D | llvm_ocaml.c | 2000 LLVMValueRef Val, value Ord, in llvm_build_atomicrmw_native()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonGenInsert.cpp | 385 const RegisterOrdering &Ord; member in __anonc146b9df0711::OrderedRegisterList
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 2878 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue()); in LowerATOMIC_FENCE() local
11869 AtomicOrdering Ord, bool IsStore, in emitLeadingFence()
11897 AtomicOrdering Ord, bool IsStore, in emitTrailingFence()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 8100 AtomicOrdering Ord, bool IsStore, in emitLeadingFence()
8110 AtomicOrdering Ord, bool IsStore, in emitTrailingFence()
|