| /external/llvm/lib/Target/AArch64/ |
| D | AArch64PBQPRegAlloc.cpp | 159 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, in addIntraChainConstraint()
243 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, in addInterChainConstraint()
363 unsigned Rd = MI.getOperand(0).getReg(); in apply() local
373 unsigned Rd = MI.getOperand(0).getReg(); in apply() local
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| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 652 unsigned Rd = fieldFromInstruction(Insn, 0, 5); in DecodeFMOVLaneInstruction() local
743 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeThreeAddrSRegInstruction() local
805 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeMoveImmInstruction() local
1296 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubERegInstruction() local
1353 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeLogicalImmInstruction() local
1384 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmInstruction() local
1423 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmTiedInstruction() local
1440 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAdrInstruction() local
1459 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeBaseAddSubImm() local
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1834 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeQADDInstruction() local
2037 unsigned Rd = fieldFromInstruction(Insn, 8, 4); in DecodeT2MOVTWInstruction() local
2061 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeArmMOVTWInstruction() local
2088 unsigned Rd = fieldFromInstruction(Insn, 16, 4); in DecodeSMLAInstruction() local
2280 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLDInstruction() local
2605 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVSTInstruction() local
2876 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD1DupInstruction() local
2923 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD2DupInstruction() local
2971 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD3DupInstruction() local
3006 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD4DupInstruction() local
[all …]
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| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1902 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1939 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1947 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
2139 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
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| /external/mesa3d/src/mesa/swrast/ |
| D | s_blend.c | 489 const GLfloat Rd = dest[i][RCOMP]; in blend_general_float() local
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| /external/v8/src/arm64/ |
| D | assembler-arm64.h | 1658 static Instr Rd(CPURegister rd) { in Rd() function
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1353 unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg(); in expandAlloca() local
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| D | HexagonInstrInfo.cpp | 960 unsigned Rd = Op0.getReg(); in expandPostRAPseudo() local
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| /external/vixl/src/vixl/a64/ |
| D | assembler-a64.h | 3765 static Instr Rd(CPURegister rd) { in Rd() function
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| /external/v8/test/mjsunit/asm/poppler/ |
| D | poppler.js | 7313 …5|0];a[k+6|0]=a[b+6|0];a[k+7|0]=a[b+7|0]}function Qd(a){a=a|0;H=a}function Rd(a){a=a|0;I=a}functio… class in anonymousFunction5c667f696a00.Md.Nd.Qd
|