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Searched defs:SchedModel (Results 1 – 21 of 21) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DHexagonMachineScheduler.h47 const TargetSchedModel *SchedModel; variable
135 const TargetSchedModel *SchedModel; member
192 const TargetSchedModel *SchedModel; variable
/external/llvm/lib/Target/AArch64/
DAArch64StorePairSuppress.cpp33 TargetSchedModel SchedModel; member in __anonc3b9fc0c0111::AArch64StorePairSuppress
DAArch64ConditionalCompares.cpp726 MCSchedModel SchedModel; member in __anonc79057fc0211::AArch64ConditionalCompares
/external/llvm/include/llvm/CodeGen/
DTargetSchedule.h35 MCSchedModel SchedModel; variable
DScheduleDAGInstrs.h95 TargetSchedModel SchedModel; variable
DMachineTraceMetrics.h73 TargetSchedModel SchedModel; variable
DMachineScheduler.h573 const TargetSchedModel *SchedModel; variable
836 const TargetSchedModel *SchedModel; variable
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.h130 bool hasLowDefLatency(const TargetSchedModel &SchedModel, in hasLowDefLatency()
/external/llvm/lib/MC/
DMCSubtargetInfo.cpp103 const MCSchedModel SchedModel = getSchedModelForCPU(CPU); in getInstrItineraryForCPU() local
/external/llvm/include/llvm/Target/
DTargetSubtargetInfo.h110 const TargetSchedModel *SchedModel) const { in resolveSchedClass()
DTargetInstrInfo.h1204 bool hasHighOperandLatency(const TargetSchedModel &SchedModel, in hasHighOperandLatency()
/external/llvm/lib/CodeGen/
DMachineCombiner.cpp42 MCSchedModel SchedModel; member in __anon5577d01f0111::MachineCombiner
DTargetInstrInfo.cpp1030 unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel &SchedModel, in defaultDefLatency()
1057 bool TargetInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel, in hasLowDefLatency()
DEarlyIfConversion.cpp592 MCSchedModel SchedModel; member in __anon59a8a6ed0211::EarlyIfConverter
DMachineTraceMetrics.cpp866 const TargetSchedModel &SchedModel, in updatePhysDepsUpwards()
927 const TargetSchedModel &SchedModel, in pushDepHeight()
DMachineLICM.cpp77 TargetSchedModel SchedModel; member in __anon89c0fe350111::MachineLICM
DMachineScheduler.cpp1692 init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) { in init()
2204 const TargetSchedModel *SchedModel) { in initResourceDelta()
DIfConversion.cpp159 TargetSchedModel SchedModel; member in __anon72ccd3d00111::IfConverter
/external/llvm/lib/Target/ARM/
DARMSubtarget.h247 MCSchedModel SchedModel; variable
DARMBaseInstrInfo.cpp4036 hasHighOperandLatency(const TargetSchedModel &SchedModel, in hasHighOperandLatency()
4057 hasLowDefLatency(const TargetSchedModel &SchedModel, in hasLowDefLatency()
/external/llvm/lib/Target/X86/
DX86InstrInfo.cpp6984 hasHighOperandLatency(const TargetSchedModel &SchedModel, in hasHighOperandLatency()