1 /* 2 * Copyright (C) 2014 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef ART_RUNTIME_ARCH_ARM64_REGISTERS_ARM64_H_ 18 #define ART_RUNTIME_ARCH_ARM64_REGISTERS_ARM64_H_ 19 20 #include <iosfwd> 21 22 namespace art { 23 namespace arm64 { 24 25 // Values for GP XRegisters - 64bit registers. 26 enum XRegister { 27 X0 = 0, 28 X1 = 1, 29 X2 = 2, 30 X3 = 3, 31 X4 = 4, 32 X5 = 5, 33 X6 = 6, 34 X7 = 7, 35 X8 = 8, 36 X9 = 9, 37 X10 = 10, 38 X11 = 11, 39 X12 = 12, 40 X13 = 13, 41 X14 = 14, 42 X15 = 15, 43 X16 = 16, 44 X17 = 17, 45 X18 = 18, 46 X19 = 19, 47 X20 = 20, 48 X21 = 21, 49 X22 = 22, 50 X23 = 23, 51 X24 = 24, 52 X25 = 25, 53 X26 = 26, 54 X27 = 27, 55 X28 = 28, 56 X29 = 29, 57 X30 = 30, 58 SP = 31, // SP and XZR are encoded in instructions using the register 59 XZR = 32, // code `31`, the context deciding which is used. We use a 60 // different enum value to distinguish between the two. 61 kNumberOfXRegisters = 33, 62 // Aliases. 63 TR = X19, // ART Thread Register - Managed Runtime (Callee Saved Reg) 64 IP0 = X16, // Used as scratch by VIXL. 65 IP1 = X17, // Used as scratch by ART JNI Assembler. 66 FP = X29, 67 LR = X30, 68 kNoRegister = -1, 69 }; 70 std::ostream& operator<<(std::ostream& os, const XRegister& rhs); 71 72 // Values for GP WRegisters - 32bit registers. 73 enum WRegister { 74 W0 = 0, 75 W1 = 1, 76 W2 = 2, 77 W3 = 3, 78 W4 = 4, 79 W5 = 5, 80 W6 = 6, 81 W7 = 7, 82 W8 = 8, 83 W9 = 9, 84 W10 = 10, 85 W11 = 11, 86 W12 = 12, 87 W13 = 13, 88 W14 = 14, 89 W15 = 15, 90 W16 = 16, 91 W17 = 17, 92 W18 = 18, 93 W19 = 19, 94 W20 = 20, 95 W21 = 21, 96 W22 = 22, 97 W23 = 23, 98 W24 = 24, 99 W25 = 25, 100 W26 = 26, 101 W27 = 27, 102 W28 = 28, 103 W29 = 29, 104 W30 = 30, 105 WSP = 31, 106 WZR = 32, 107 kNumberOfWRegisters = 33, 108 kNoWRegister = -1, 109 }; 110 std::ostream& operator<<(std::ostream& os, const WRegister& rhs); 111 112 // Values for FP DRegisters - double precision floating point. 113 enum DRegister { 114 D0 = 0, 115 D1 = 1, 116 D2 = 2, 117 D3 = 3, 118 D4 = 4, 119 D5 = 5, 120 D6 = 6, 121 D7 = 7, 122 D8 = 8, 123 D9 = 9, 124 D10 = 10, 125 D11 = 11, 126 D12 = 12, 127 D13 = 13, 128 D14 = 14, 129 D15 = 15, 130 D16 = 16, 131 D17 = 17, 132 D18 = 18, 133 D19 = 19, 134 D20 = 20, 135 D21 = 21, 136 D22 = 22, 137 D23 = 23, 138 D24 = 24, 139 D25 = 25, 140 D26 = 26, 141 D27 = 27, 142 D28 = 28, 143 D29 = 29, 144 D30 = 30, 145 D31 = 31, 146 kNumberOfDRegisters = 32, 147 kNoDRegister = -1, 148 }; 149 std::ostream& operator<<(std::ostream& os, const DRegister& rhs); 150 151 // Values for FP SRegisters - single precision floating point. 152 enum SRegister { 153 S0 = 0, 154 S1 = 1, 155 S2 = 2, 156 S3 = 3, 157 S4 = 4, 158 S5 = 5, 159 S6 = 6, 160 S7 = 7, 161 S8 = 8, 162 S9 = 9, 163 S10 = 10, 164 S11 = 11, 165 S12 = 12, 166 S13 = 13, 167 S14 = 14, 168 S15 = 15, 169 S16 = 16, 170 S17 = 17, 171 S18 = 18, 172 S19 = 19, 173 S20 = 20, 174 S21 = 21, 175 S22 = 22, 176 S23 = 23, 177 S24 = 24, 178 S25 = 25, 179 S26 = 26, 180 S27 = 27, 181 S28 = 28, 182 S29 = 29, 183 S30 = 30, 184 S31 = 31, 185 kNumberOfSRegisters = 32, 186 kNoSRegister = -1, 187 }; 188 std::ostream& operator<<(std::ostream& os, const SRegister& rhs); 189 190 } // namespace arm64 191 } // namespace art 192 193 #endif // ART_RUNTIME_ARCH_ARM64_REGISTERS_ARM64_H_ 194