| /art/runtime/interpreter/mterp/mips/ |
| D | header.S | 230 #define FETCH_ADVANCE_INST_RB(rd) addu rPC, rPC, rd; \ argument
239 #define FETCH(rd, _count) lhu rd, ((_count) * 2)(rPC) argument
240 #define FETCH_S(rd, _count) lh rd, ((_count) * 2)(rPC) argument
247 #define FETCH_B(rd, _count, _byte) lbu rd, ((_count) * 2 + _byte)(rPC) argument
252 #define GET_INST_OPCODE(rd) and rd, rINST, 0xFF argument
262 #define GOTO_OPCODE(rd) sll rd, rd, ${handler_size_bits}; \ argument
266 #define GOTO_OPCODE_BASE(_base, rd) sll rd, rd, ${handler_size_bits}; \ argument
273 #define GET_VREG(rd, rix) LOAD_eas2(rd, rFP, rix) argument
275 #define GET_VREG_F(rd, rix) EAS2(AT, rFP, rix); \ argument
278 #define SET_VREG(rd, rix) .set noat; \ argument
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| /art/compiler/utils/arm/ |
| D | assembler_arm32.cc | 65 void Arm32Assembler::and_(Register rd, Register rn, const ShifterOperand& so, in and_()
71 void Arm32Assembler::eor(Register rd, Register rn, const ShifterOperand& so, in eor()
77 void Arm32Assembler::sub(Register rd, Register rn, const ShifterOperand& so, in sub()
82 void Arm32Assembler::rsb(Register rd, Register rn, const ShifterOperand& so, in rsb()
87 void Arm32Assembler::add(Register rd, Register rn, const ShifterOperand& so, in add()
93 void Arm32Assembler::adc(Register rd, Register rn, const ShifterOperand& so, in adc()
99 void Arm32Assembler::sbc(Register rd, Register rn, const ShifterOperand& so, in sbc()
105 void Arm32Assembler::rsc(Register rd, Register rn, const ShifterOperand& so, in rsc()
133 void Arm32Assembler::orr(Register rd, Register rn, const ShifterOperand& so, in orr()
148 void Arm32Assembler::mov(Register rd, const ShifterOperand& so, in mov()
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| D | assembler_thumb2.cc | 383 inline int32_t Thumb2Assembler::MovwEncoding32(Register rd, int32_t value) { in MovwEncoding32()
393 inline int32_t Thumb2Assembler::MovtEncoding32(Register rd, int32_t value) { in MovtEncoding32()
399 inline int32_t Thumb2Assembler::MovModImmEncoding32(Register rd, int32_t value) { in MovModImmEncoding32()
478 inline int16_t Thumb2Assembler::AdrEncoding16(Register rd, int32_t offset) { in AdrEncoding16()
485 inline int32_t Thumb2Assembler::AdrEncoding32(Register rd, int32_t offset) { in AdrEncoding32()
542 void Thumb2Assembler::and_(Register rd, Register rn, const ShifterOperand& so, in and_()
548 void Thumb2Assembler::eor(Register rd, Register rn, const ShifterOperand& so, in eor()
554 void Thumb2Assembler::sub(Register rd, Register rn, const ShifterOperand& so, in sub()
560 void Thumb2Assembler::rsb(Register rd, Register rn, const ShifterOperand& so, in rsb()
566 void Thumb2Assembler::add(Register rd, Register rn, const ShifterOperand& so, in add()
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| D | assembler_arm.h | 890 bool ShifterOperandCanHold(Register rd, in ShifterOperandCanHold()
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64.cc | 91 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, in EmitR()
105 void Mips64Assembler::EmitRsd(int opcode, GpuRegister rs, GpuRegister rd, in EmitRsd()
118 void Mips64Assembler::EmitRtd(int opcode, GpuRegister rt, GpuRegister rd, in EmitRtd()
179 void Mips64Assembler::Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Addu()
187 void Mips64Assembler::Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Daddu()
195 void Mips64Assembler::Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Subu()
199 void Mips64Assembler::Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in Dsubu()
203 void Mips64Assembler::MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in MulR6()
207 void Mips64Assembler::MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in MuhR6()
211 void Mips64Assembler::DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in DivR6()
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| /art/compiler/utils/mips/ |
| D | assembler_mips.cc | 125 void MipsAssembler::EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct) { in EmitR()
186 void MipsAssembler::Addu(Register rd, Register rs, Register rt) { in Addu()
194 void MipsAssembler::Subu(Register rd, Register rs, Register rt) { in Subu()
218 void MipsAssembler::MulR2(Register rd, Register rs, Register rt) { in MulR2()
223 void MipsAssembler::DivR2(Register rd, Register rs, Register rt) { in DivR2()
229 void MipsAssembler::ModR2(Register rd, Register rs, Register rt) { in ModR2()
235 void MipsAssembler::DivuR2(Register rd, Register rs, Register rt) { in DivuR2()
241 void MipsAssembler::ModuR2(Register rd, Register rs, Register rt) { in ModuR2()
247 void MipsAssembler::MulR6(Register rd, Register rs, Register rt) { in MulR6()
252 void MipsAssembler::MuhR6(Register rd, Register rs, Register rt) { in MuhR6()
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| /art/runtime/interpreter/mterp/out/ |
| D | mterp_mips.S | 237 #define FETCH_ADVANCE_INST_RB(rd) addu rPC, rPC, rd; \ argument
246 #define FETCH(rd, _count) lhu rd, ((_count) * 2)(rPC) argument
247 #define FETCH_S(rd, _count) lh rd, ((_count) * 2)(rPC) argument
254 #define FETCH_B(rd, _count, _byte) lbu rd, ((_count) * 2 + _byte)(rPC) argument
259 #define GET_INST_OPCODE(rd) and rd, rINST, 0xFF argument
269 #define GOTO_OPCODE(rd) sll rd, rd, 7; \ argument
273 #define GOTO_OPCODE_BASE(_base, rd) sll rd, rd, 7; \ argument
280 #define GET_VREG(rd, rix) LOAD_eas2(rd, rFP, rix) argument
282 #define GET_VREG_F(rd, rix) EAS2(AT, rFP, rix); \ argument
285 #define SET_VREG(rd, rix) .set noat; \ argument
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| /art/disassembler/ |
| D | disassembler_mips.cc | 416 uint32_t rd = (instruction >> 11) & 0x1f; // R-type. in Dump() local
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| D | disassembler_arm.cc | 1794 ThumbRegister rd(instr, 8); in DumpThumb16() local
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| /art/compiler/utils/arm64/ |
| D | assembler_arm64.cc | 77 void Arm64Assembler::AddConstant(XRegister rd, int32_t value, Condition cond) { in AddConstant()
81 void Arm64Assembler::AddConstant(XRegister rd, XRegister rn, int32_t value, in AddConstant()
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| /art/compiler/utils/x86_64/ |
| D | assembler_x86_64_test.cc | 55 std::random_device rd; in TEST() local
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