1 //=- HexagonFrameLowering.h - Define frame lowering for Hexagon --*- C++ -*--=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H 11 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H 12 13 #include "Hexagon.h" 14 #include "llvm/Target/TargetFrameLowering.h" 15 16 namespace llvm { 17 18 class HexagonInstrInfo; 19 class HexagonRegisterInfo; 20 21 class HexagonFrameLowering : public TargetFrameLowering { 22 public: HexagonFrameLowering()23 explicit HexagonFrameLowering() 24 : TargetFrameLowering(StackGrowsDown, 8, 0, 1, true) {} 25 26 // All of the prolog/epilog functionality, including saving and restoring 27 // callee-saved registers is handled in emitPrologue. This is to have the 28 // logic for shrink-wrapping in one place. 29 void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const 30 override; emitEpilogue(MachineFunction & MF,MachineBasicBlock & MBB)31 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const 32 override {} spillCalleeSavedRegisters(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,const std::vector<CalleeSavedInfo> & CSI,const TargetRegisterInfo * TRI)33 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 34 MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, 35 const TargetRegisterInfo *TRI) const override { 36 return true; 37 } restoreCalleeSavedRegisters(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,const std::vector<CalleeSavedInfo> & CSI,const TargetRegisterInfo * TRI)38 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 39 MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, 40 const TargetRegisterInfo *TRI) const override { 41 return true; 42 } 43 44 void eliminateCallFramePseudoInstr(MachineFunction &MF, 45 MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const override; 46 void processFunctionBeforeFrameFinalized(MachineFunction &MF, 47 RegScavenger *RS = nullptr) const override; 48 void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, 49 RegScavenger *RS) const override; 50 targetHandlesStackFrameRounding()51 bool targetHandlesStackFrameRounding() const override { 52 return true; 53 } 54 int getFrameIndexReference(const MachineFunction &MF, int FI, 55 unsigned &FrameReg) const override; 56 bool hasFP(const MachineFunction &MF) const override; 57 getCalleeSavedSpillSlots(unsigned & NumEntries)58 const SpillSlot *getCalleeSavedSpillSlots(unsigned &NumEntries) 59 const override { 60 static const SpillSlot Offsets[] = { 61 { Hexagon::R17, -4 }, { Hexagon::R16, -8 }, { Hexagon::D8, -8 }, 62 { Hexagon::R19, -12 }, { Hexagon::R18, -16 }, { Hexagon::D9, -16 }, 63 { Hexagon::R21, -20 }, { Hexagon::R20, -24 }, { Hexagon::D10, -24 }, 64 { Hexagon::R23, -28 }, { Hexagon::R22, -32 }, { Hexagon::D11, -32 }, 65 { Hexagon::R25, -36 }, { Hexagon::R24, -40 }, { Hexagon::D12, -40 }, 66 { Hexagon::R27, -44 }, { Hexagon::R26, -48 }, { Hexagon::D13, -48 } 67 }; 68 NumEntries = array_lengthof(Offsets); 69 return Offsets; 70 } 71 72 bool assignCalleeSavedSpillSlots(MachineFunction &MF, 73 const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI) 74 const override; 75 76 bool needsAligna(const MachineFunction &MF) const; 77 const MachineInstr *getAlignaInstr(const MachineFunction &MF) const; 78 79 void insertCFIInstructions(MachineFunction &MF) const; 80 81 private: 82 typedef std::vector<CalleeSavedInfo> CSIVect; 83 84 void expandAlloca(MachineInstr *AI, const HexagonInstrInfo &TII, 85 unsigned SP, unsigned CF) const; 86 void insertPrologueInBlock(MachineBasicBlock &MBB) const; 87 void insertEpilogueInBlock(MachineBasicBlock &MBB) const; 88 bool insertCSRSpillsInBlock(MachineBasicBlock &MBB, const CSIVect &CSI, 89 const HexagonRegisterInfo &HRI) const; 90 bool insertCSRRestoresInBlock(MachineBasicBlock &MBB, const CSIVect &CSI, 91 const HexagonRegisterInfo &HRI) const; 92 void insertCFIInstructionsAt(MachineBasicBlock &MBB, 93 MachineBasicBlock::iterator At) const; 94 95 void adjustForCalleeSavedRegsSpillCall(MachineFunction &MF) const; 96 bool replacePredRegPseudoSpillCode(MachineFunction &MF) const; 97 bool replaceVecPredRegPseudoSpillCode(MachineFunction &MF) const; 98 99 void findShrunkPrologEpilog(MachineFunction &MF, MachineBasicBlock *&PrologB, 100 MachineBasicBlock *&EpilogB) const; 101 102 bool shouldInlineCSR(llvm::MachineFunction &MF, const CSIVect &CSI) const; 103 bool useSpillFunction(MachineFunction &MF, const CSIVect &CSI) const; 104 bool useRestoreFunction(MachineFunction &MF, const CSIVect &CSI) const; 105 }; 106 107 } // End llvm namespace 108 109 #endif 110