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Searched refs:R5 (Results 1 – 9 of 9) sorted by relevance

/art/runtime/arch/arm/
Dregisters_arm.h32 R5 = 5, enumerator
Dquick_method_frame_info_arm.h31 (1 << art::arm::R5) | (1 << art::arm::R6) | (1 << art::arm::R7) | (1 << art::arm::R8) |
/art/compiler/jni/quick/arm/
Dcalling_convention_arm.cc227 callee_save_regs_.push_back(ArmManagedRegister::FromCoreRegister(R5)); in ArmJniCallingConvention()
242 result = 1 << R5 | 1 << R6 | 1 << R7 | 1 << R8 | 1 << R10 | 1 << R11 | 1 << LR; in CoreSpillMask()
/art/compiler/utils/arm/
Dassembler_thumb2_test.cc54 new arm::Register(arm::R5), in SetUpHelpers()
186 __ ldrexd(arm::R5, arm::R3, arm::R7); in TEST_F()
200 __ strexd(arm::R9, arm::R5, arm::R3, arm::R7); in TEST_F()
289 __ StoreToOffset(type, arm::IP, arm::R5, offset); in TEST_F()
305 __ StoreToOffset(type, arm::IP, arm::R5, offset); in TEST_F()
338 __ StoreToOffset(type, arm::R11, arm::R5, offset); in TEST_F()
357 __ StoreToOffset(type, arm::R11, arm::R5, offset); in TEST_F()
Dassembler_arm32_test.cc88 new arm::Register(arm::R5), in SetUpHelpers()
150 shifter_operands_.push_back(arm::ShifterOperand(arm::R5)); in SetUpHelpers()
Dassembler_thumb2.cc3751 tmp_reg = (base != R5) ? R5 : R6; in StoreToOffset()
3781 CHECK((tmp_reg == R5) || (tmp_reg == R6)); in StoreToOffset()
Dmanaged_register_arm_test.cc272 EXPECT_EQ(R5, reg.AsRegisterPairHigh()); in TEST()
/art/compiler/utils/
Dassembler_thumb_test.cc783 __ ldm(DB_W, R4, (1 << R5)); in TEST_F()
797 __ stm(IA_W, R4, (1 << R5)); in TEST_F()
798 __ stm(IA, R4, (1 << R5)); in TEST_F()
/art/compiler/optimizing/
Dcode_generator_arm.cc50 static constexpr Register kCoreAlwaysSpillRegister = R5;
52 { R5, R6, R7, R8, R10, R11, LR };