Searched refs:RelOffset (Results 1 – 11 of 11) sorted by relevance
/art/compiler/debug/dwarf/ |
D | dwarf_test.cc | 113 opcodes.RelOffset(Reg(0), 0); // push R0 in TEST_F() 115 opcodes.RelOffset(Reg(1), 4); // push R1 in TEST_F() 159 opcodes.RelOffset(Reg::X86_64Core(i), 0); in TEST_F()
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D | debug_frame_opcode_writer.h | 73 void ALWAYS_INLINE RelOffset(Reg reg, int offset) { in RelOffset() function 92 RelOffset(Reg(reg_base.num() + i), offset); in RelOffsetForMany()
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/art/compiler/utils/arm64/ |
D | assembler_arm64.cc | 655 cfi_.RelOffset(DWARFReg(dst0), offset); in SpillRegisters() 656 cfi_.RelOffset(DWARFReg(dst1), offset + size); in SpillRegisters() 662 cfi_.RelOffset(DWARFReg(dst0), offset); in SpillRegisters()
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/art/compiler/utils/mips64/ |
D | assembler_mips64.cc | 1992 cfi_.RelOffset(DWARFReg(RA), stack_offset); in BuildFrame() 1997 cfi_.RelOffset(DWARFReg(reg), stack_offset); in BuildFrame()
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/art/compiler/utils/x86_64/ |
D | assembler_x86_64.cc | 2654 cfi_.RelOffset(DWARFReg(spill.AsCpuRegister().AsRegister()), 0); in BuildFrame() 2671 cfi_.RelOffset(DWARFReg(spill.AsXmmRegister().AsFloatRegister()), offset); in BuildFrame()
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/art/compiler/utils/mips/ |
D | assembler_mips.cc | 2453 cfi_.RelOffset(DWARFReg(RA), stack_offset); in BuildFrame() 2458 cfi_.RelOffset(DWARFReg(reg), stack_offset); in BuildFrame()
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/art/compiler/optimizing/ |
D | code_generator_mips64.cc | 557 __ cfi().RelOffset(DWARFReg(reg), ofs); in GenerateFrameEntry() 566 __ cfi().RelOffset(DWARFReg(reg), ofs); in GenerateFrameEntry()
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D | code_generator_x86_64.cc | 1066 __ cfi().RelOffset(DWARFReg(reg), 0); in GenerateFrameEntry() 1080 __ cfi().RelOffset(DWARFReg(kFpuCalleeSaves[i]), offset); in GenerateFrameEntry()
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D | code_generator_mips.cc | 710 __ cfi().RelOffset(DWARFReg(reg), ofs); in GenerateFrameEntry()
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D | code_generator_x86.cc | 863 __ cfi().RelOffset(DWARFReg(reg), 0); in GenerateFrameEntry()
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/art/compiler/utils/x86/ |
D | assembler_x86.cc | 1939 cfi_.RelOffset(DWARFReg(spill), 0); in BuildFrame()
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