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Searched refs:S1 (Results 1 – 22 of 22) sorted by relevance

/art/runtime/arch/mips/
Dregisters_mips.h47 S1 = 17, enumerator
62 TR = S1, // ART Thread Register
Dquick_method_frame_info_mips.h36 (1 << art::mips::S0) | (1 << art::mips::S1);
/art/runtime/arch/mips64/
Dregisters_mips64.h47 S1 = 17, enumerator
62 TR = S1, // ART Thread Register
Dquick_method_frame_info_mips64.h37 (1 << art::mips64::S0) | (1 << art::mips64::S1);
/art/compiler/utils/arm/
Dmanaged_register_arm_test.cc78 reg = ArmManagedRegister::FromSRegister(S1); in TEST()
85 EXPECT_EQ(S1, reg.AsSRegister()); in TEST()
135 EXPECT_EQ(S1, reg.AsOverlappingDRegisterHigh()); in TEST()
312 EXPECT_TRUE(!reg_R1.Equals(ArmManagedRegister::FromSRegister(S1))); in TEST()
322 EXPECT_TRUE(!reg_R8.Equals(ArmManagedRegister::FromSRegister(S1))); in TEST()
331 EXPECT_TRUE(!reg_S0.Equals(ArmManagedRegister::FromSRegister(S1))); in TEST()
336 ArmManagedRegister reg_S1 = ArmManagedRegister::FromSRegister(S1); in TEST()
341 EXPECT_TRUE(reg_S1.Equals(ArmManagedRegister::FromSRegister(S1))); in TEST()
465 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S1))); in TEST()
487 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S1))); in TEST()
[all …]
/art/compiler/utils/arm64/
Dmanaged_register_arm64_test.cc181 sreg = Arm64ManagedRegister::FromSRegister(S1); in TEST()
189 EXPECT_EQ(S1, reg.AsOverlappingSRegister()); in TEST()
294 EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
310 EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
320 EXPECT_TRUE(!reg_W12.Equals(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
328 EXPECT_TRUE(!reg_S0.Equals(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
332 Arm64ManagedRegister reg_S1 = Arm64ManagedRegister::FromSRegister(S1); in TEST()
338 EXPECT_TRUE(reg_S1.Equals(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
387 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
409 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1))); in TEST()
[all …]
/art/runtime/arch/arm/
Dregisters_arm.h58 S1 = 1, enumerator
Dcontext_arm.cc82 fprs_[S1] = nullptr; in SmashCallerSaves()
Dquick_method_frame_info_arm.h41 (1 << art::arm::S0) | (1 << art::arm::S1) | (1 << art::arm::S2) | (1 << art::arm::S3) |
/art/compiler/utils/
Dassembler_thumb_test.cc974 __ vmovs(S1, 1.0); in TEST_F()
977 __ vmovs(S1, S2); in TEST_F()
985 __ vadds(S0, S1, S2); in TEST_F()
986 __ vsubs(S0, S1, S2); in TEST_F()
987 __ vmuls(S0, S1, S2); in TEST_F()
988 __ vmlas(S0, S1, S2); in TEST_F()
989 __ vmlss(S0, S1, S2); in TEST_F()
990 __ vdivs(S0, S1, S2); in TEST_F()
991 __ vabss(S0, S1); in TEST_F()
992 __ vnegs(S0, S1); in TEST_F()
[all …]
/art/runtime/arch/arm64/
Dregisters_arm64.h154 S1 = 1, enumerator
/art/compiler/trampolines/
Dtrampoline_compiler.cc134 __ LoadFromOffset(kLoadWord, T9, S1, offset.Int32Value()); in CreateTrampoline()
166 __ LoadFromOffset(kLoadDoubleword, T9, S1, offset.Int32Value()); in CreateTrampoline()
/art/compiler/optimizing/
Dcode_generator_arm.h40 { S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15 };
48 static constexpr SRegister kRuntimeParameterFpuRegisters[] = { S0, S1, S2, S3 };
124 ? Location::FpuRegisterPairLocation(S0, S1) in GetFpuLocation()
Dcode_generator_mips64.h55 { S0, S1, S2, S3, S4, S5, S6, S7, GP, S8, RA }; // TODO: review
Dcode_generator_mips.h55 { S0, S1, S2, S3, S4, S5, S6, S7, FP, RA };
Dcode_generator_arm.cc1053 return Location::FpuRegisterPairLocation(S0, S1); in GetReturnLocation()
3010 locations->SetOut(Location::Location::FpuRegisterPairLocation(S0, S1)); in VisitRem()
/art/compiler/jni/quick/arm64/
Dcalling_convention_arm64.cc38 S0, S1, S2, S3, S4, S5, S6, S7
/art/compiler/utils/mips64/
Dassembler_mips64.cc2118 StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), S1, thr_offs.Int32Value()); in StoreStackOffsetToThread64()
2122 StoreToOffset(kStoreDoubleword, SP, S1, thr_offs.Int32Value()); in StoreStackPointerToThread64()
2141 return EmitLoad(mdest, S1, src.Int32Value(), size); in LoadFromThread64()
2177 LoadFromOffset(kLoadDoubleword, dest.AsGpuRegister(), S1, offs.Int32Value()); in LoadRawPtrFromThread64()
2223 LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), S1, thr_offs.Int32Value()); in CopyRawPtrFromThread64()
2235 S1, thr_offs.Int32Value()); in CopyRawPtrToThread64()
2437 Move(tr.AsMips64().AsGpuRegister(), S1); in GetCurrentThread()
2442 StoreToOffset(kStoreDoubleword, S1, SP, offset.Int32Value()); in GetCurrentThread()
2450 S1, in ExceptionPoll()
2467 S1, in EmitExceptionPoll()
Dassembler_mips64_test.cc98 registers_.push_back(new mips64::GpuRegister(mips64::S1)); in SetUpHelpers()
131 secondary_register_names_.emplace(mips64::GpuRegister(mips64::S1), "s1"); in SetUpHelpers()
/art/compiler/jni/quick/arm/
Dcalling_convention_arm.cc31 S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
/art/compiler/utils/mips/
Dassembler_mips.cc2579 StoreToOffset(kStoreWord, scratch.AsCoreRegister(), S1, dest.Int32Value()); in StoreImmediateToThread32()
2589 S1, thr_offs.Int32Value()); in StoreStackOffsetToThread32()
2593 StoreToOffset(kStoreWord, SP, S1, thr_offs.Int32Value()); in StoreStackPointerToThread32()
2611 return EmitLoad(mdest, S1, src.Int32Value(), size); in LoadFromThread32()
2642 LoadFromOffset(kLoadWord, dest.AsCoreRegister(), S1, offs.Int32Value()); in LoadRawPtrFromThread32()
2699 S1, thr_offs.Int32Value()); in CopyRawPtrFromThread32()
2712 S1, thr_offs.Int32Value()); in CopyRawPtrToThread32()
2884 Move(tr.AsMips().AsCoreRegister(), S1); in GetCurrentThread()
2889 StoreToOffset(kStoreWord, S1, SP, offset.Int32Value()); in GetCurrentThread()
2896 S1, Thread::ExceptionOffset<kMipsWordSize>().Int32Value()); in ExceptionPoll()
[all …]
Dassembler_mips_test.cc74 registers_.push_back(new mips::Register(mips::S1)); in SetUpHelpers()
107 secondary_register_names_.emplace(mips::Register(mips::S1), "s1"); in SetUpHelpers()