| /art/runtime/arch/arm/ |
| D | registers_arm.h | 59 S2 = 2, enumerator
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| D | context_arm.cc | 83 fprs_[S2] = nullptr; in SmashCallerSaves()
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| D | quick_method_frame_info_arm.h | 41 (1 << art::arm::S0) | (1 << art::arm::S1) | (1 << art::arm::S2) | (1 << art::arm::S3) |
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| /art/compiler/jni/quick/mips64/ |
| D | calling_convention_mips64.cc | 129 callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(S2)); in Mips64JniCallingConvention()
142 result = 1 << S2 | 1 << S3 | 1 << S4 | 1 << S5 | 1 << S6 | 1 << S7 | 1 << GP | 1 << S8 | 1 << RA; in CoreSpillMask()
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| /art/compiler/utils/arm/ |
| D | managed_register_arm_test.cc | 146 EXPECT_EQ(S2, reg.AsOverlappingDRegisterLow()); in TEST()
148 EXPECT_TRUE(reg.Equals(ArmManagedRegister::FromSRegisterPair(S2))); in TEST()
466 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S2))); in TEST()
488 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S2))); in TEST()
510 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S2))); in TEST()
532 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S2))); in TEST()
554 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S2))); in TEST()
576 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S2))); in TEST()
598 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S2))); in TEST()
620 EXPECT_TRUE(!reg.Overlaps(ArmManagedRegister::FromSRegister(S2))); in TEST()
[all …]
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| /art/runtime/arch/mips/ |
| D | registers_mips.h | 48 S2 = 18, enumerator
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| D | quick_method_frame_info_mips.h | 31 (1 << art::mips::S2) | (1 << art::mips::S3) | (1 << art::mips::S4) | (1 << art::mips::S5) |
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| /art/runtime/arch/mips64/ |
| D | registers_mips64.h | 48 S2 = 18, enumerator
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| D | quick_method_frame_info_mips64.h | 29 (1 << art::mips64::S2) | (1 << art::mips64::S3) | (1 << art::mips64::S4) |
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| /art/compiler/jni/quick/mips/ |
| D | calling_convention_mips.cc | 165 callee_save_regs_.push_back(MipsManagedRegister::FromCoreRegister(S2)); in MipsJniCallingConvention()
177 result = 1 << S2 | 1 << S3 | 1 << S4 | 1 << S5 | 1 << S6 | 1 << S7 | 1 << FP | 1 << RA; in CoreSpillMask()
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| /art/compiler/utils/ |
| D | assembler_thumb_test.cc | 977 __ vmovs(S1, S2); in TEST_F()
985 __ vadds(S0, S1, S2); in TEST_F()
986 __ vsubs(S0, S1, S2); in TEST_F()
987 __ vmuls(S0, S1, S2); in TEST_F()
988 __ vmlas(S0, S1, S2); in TEST_F()
989 __ vmlss(S0, S1, S2); in TEST_F()
990 __ vdivs(S0, S1, S2); in TEST_F()
1009 __ vcvtsd(S2, D2); in TEST_F()
1010 __ vcvtds(D2, S2); in TEST_F()
1012 __ vcvtis(S1, S2); in TEST_F()
[all …]
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| /art/runtime/arch/arm64/ |
| D | registers_arm64.h | 155 S2 = 2, enumerator
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| /art/compiler/utils/arm64/ |
| D | managed_register_arm64_test.cc | 388 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2))); in TEST()
410 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2))); in TEST()
432 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2))); in TEST()
452 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2))); in TEST()
470 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2))); in TEST()
491 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2))); in TEST()
512 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2))); in TEST()
535 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2))); in TEST()
558 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2))); in TEST()
581 EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2))); in TEST()
[all …]
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| /art/compiler/jni/quick/arm64/ |
| D | calling_convention_arm64.cc | 38 S0, S1, S2, S3, S4, S5, S6, S7
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| /art/compiler/optimizing/ |
| D | code_generator_arm.h | 40 { S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15 };
48 static constexpr SRegister kRuntimeParameterFpuRegisters[] = { S0, S1, S2, S3 };
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| D | code_generator_mips64.h | 55 { S0, S1, S2, S3, S4, S5, S6, S7, GP, S8, RA }; // TODO: review
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| D | code_generator_mips.h | 55 { S0, S1, S2, S3, S4, S5, S6, S7, FP, RA };
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| /art/compiler/jni/quick/arm/ |
| D | calling_convention_arm.cc | 31 S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
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| /art/compiler/utils/mips/ |
| D | assembler_mips_test.cc | 75 registers_.push_back(new mips::Register(mips::S2)); in SetUpHelpers()
108 secondary_register_names_.emplace(mips::Register(mips::S2), "s2"); in SetUpHelpers()
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64_test.cc | 99 registers_.push_back(new mips64::GpuRegister(mips64::S2)); in SetUpHelpers()
132 secondary_register_names_.emplace(mips64::GpuRegister(mips64::S2), "s2"); in SetUpHelpers()
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