Home
last modified time | relevance | path

Searched refs:S5 (Results 1 – 18 of 18) sorted by relevance

/art/runtime/arch/arm/
Dregisters_arm.h62 S5 = 5, enumerator
Dcontext_arm.cc86 fprs_[S5] = nullptr; in SmashCallerSaves()
Dquick_method_frame_info_arm.h42 (1 << art::arm::S4) | (1 << art::arm::S5) | (1 << art::arm::S6) | (1 << art::arm::S7) |
/art/compiler/jni/quick/mips64/
Dcalling_convention_mips64.cc132 callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(S5)); in Mips64JniCallingConvention()
142 result = 1 << S2 | 1 << S3 | 1 << S4 | 1 << S5 | 1 << S6 | 1 << S7 | 1 << GP | 1 << S8 | 1 << RA; in CoreSpillMask()
/art/runtime/arch/mips/
Dregisters_mips.h51 S5 = 21, enumerator
Dquick_method_frame_info_mips.h31 (1 << art::mips::S2) | (1 << art::mips::S3) | (1 << art::mips::S4) | (1 << art::mips::S5) |
/art/runtime/arch/mips64/
Dregisters_mips64.h51 S5 = 21, enumerator
Dquick_method_frame_info_mips64.h30 (1 << art::mips64::S5) | (1 << art::mips64::S6) | (1 << art::mips64::S7) |
/art/compiler/jni/quick/mips/
Dcalling_convention_mips.cc168 callee_save_regs_.push_back(MipsManagedRegister::FromCoreRegister(S5)); in MipsJniCallingConvention()
177 result = 1 << S2 | 1 << S3 | 1 << S4 | 1 << S5 | 1 << S6 | 1 << S7 | 1 << FP | 1 << RA; in CoreSpillMask()
/art/runtime/arch/arm64/
Dregisters_arm64.h158 S5 = 5, enumerator
/art/compiler/jni/quick/arm64/
Dcalling_convention_arm64.cc38 S0, S1, S2, S3, S4, S5, S6, S7
/art/compiler/jni/quick/arm/
Dcalling_convention_arm.cc31 S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
/art/compiler/optimizing/
Dcode_generator_mips64.h55 { S0, S1, S2, S3, S4, S5, S6, S7, GP, S8, RA }; // TODO: review
Dcode_generator_mips.h55 { S0, S1, S2, S3, S4, S5, S6, S7, FP, RA };
Dcode_generator_arm.h40 { S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15 };
/art/compiler/utils/arm64/
Dmanaged_register_arm64_test.cc231 reg = Arm64ManagedRegister::FromSRegister(S5); in TEST()
239 EXPECT_EQ(S5, reg.AsSRegister()); in TEST()
241 EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromSRegister(S5))); in TEST()
710 EXPECT_TRUE(vixl::s5.Is(Arm64Assembler::reg_s(S5))); in TEST()
/art/compiler/utils/mips/
Dassembler_mips_test.cc78 registers_.push_back(new mips::Register(mips::S5)); in SetUpHelpers()
111 secondary_register_names_.emplace(mips::Register(mips::S5), "s5"); in SetUpHelpers()
/art/compiler/utils/mips64/
Dassembler_mips64_test.cc102 registers_.push_back(new mips64::GpuRegister(mips64::S5)); in SetUpHelpers()
135 secondary_register_names_.emplace(mips64::GpuRegister(mips64::S5), "s5"); in SetUpHelpers()