| /art/compiler/utils/mips/ |
| D | assembler_mips.cc | 474 void MipsAssembler::Sw(Register rt, Register rs, uint16_t imm16) { in Sw() function in art::mips::MipsAssembler
1345 Sw(rs, SP, 0); in Push()
1400 Sw(temp, base, offset); in StoreConst32ToOffset()
1418 Sw(ZERO, base, offset); in StoreConst64ToOffset()
1421 Sw(temp, base, offset); in StoreConst64ToOffset()
1424 Sw(ZERO, base, offset + kMipsWordSize); in StoreConst64ToOffset()
1429 Sw(temp, base, offset + kMipsWordSize); in StoreConst64ToOffset()
2385 Sw(reg, base, offset); in StoreToOffset()
2390 Sw(reg, base, offset); in StoreToOffset()
2391 Sw(static_cast<Register>(reg + 1), base, offset + kMipsWordSize); in StoreToOffset()
[all …]
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| D | assembler_mips_test.cc | 484 TEST_F(AssemblerMIPSTest, Sw) { in TEST_F() argument
485 DriverStr(RepeatRRIb(&mips::MipsAssembler::Sw, -16, "sw ${reg1}, {imm}(${reg2})"), "Sw"); in TEST_F()
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| D | assembler_mips.h | 192 void Sw(Register rt, Register rs, uint16_t imm16);
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| /art/compiler/optimizing/ |
| D | intrinsics_mips.cc | 1430 __ Sw(val, adr, 0); in VisitMemoryPokeIntNative() local
1449 __ Sw(val_lo, adr, 0); in VisitMemoryPokeLongNative() local
1450 __ Sw(val_hi, adr, 4); in VisitMemoryPokeLongNative() local
1627 __ Sw(value, TMP, 0); in GenUnsafePut() local
1637 __ Sw(value_lo, TMP, 0); in GenUnsafePut() local
1638 __ Sw(value_hi, TMP, 4); in GenUnsafePut() local
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| D | intrinsics_mips64.cc | 889 __ Sw(val, adr, 00); in VisitMemoryPokeIntNative() local
1057 __ Sw(value, TMP, 0); in GenUnsafePut() local
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| D | code_generator_mips.cc | 709 __ Sw(reg, SP, ofs); in GenerateFrameEntry() local
726 __ Sw(TMP, SP, ofs + 4); in GenerateFrameEntry() local
742 __ Sw(kMethodRegisterArgument, SP, kCurrentMethodStackOffset); in GenerateFrameEntry() local
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64.cc | 473 void Mips64Assembler::Sw(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Sw() function in art::mips64::Mips64Assembler
1926 Sw(reg, base, offset); in StoreToOffset()
1931 Sw(reg, base, offset); in StoreToOffset()
1933 Sw(TMP2, base, offset + kMips64WordSize); in StoreToOffset()
1964 Sw(TMP2, base, offset + kMips64WordSize); in StoreFpuToOffset()
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| D | assembler_mips64.h | 199 void Sw(GpuRegister rt, GpuRegister rs, uint16_t imm16);
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