| /art/compiler/optimizing/ |
| D | intrinsics_mips.cc | 265 __ Sll(TMP, in, 24); in GenReverse()
266 __ Sra(TMP, TMP, 16); in GenReverse()
269 __ Or(out, out, TMP); in GenReverse()
281 __ Sll(TMP, in, 16); in GenReverse()
283 __ Or(out, out, TMP); in GenReverse()
286 __ And(TMP, out, AT); in GenReverse()
287 __ Sll(TMP, TMP, 8); in GenReverse()
290 __ Or(out, out, TMP); in GenReverse()
297 __ And(TMP, out, AT); in GenReverse()
298 __ Sll(TMP, TMP, 4); in GenReverse()
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| D | code_generator_mips.cc | 542 __ Move(TMP, r2); in EmitSwap()
544 __ Move(r1, TMP); in EmitSwap()
566 __ Move(TMP, r2); in EmitSwap()
568 __ Mtc1(TMP, f1); in EmitSwap()
573 __ Move(TMP, r2); in EmitSwap()
575 __ Move(r1, TMP); in EmitSwap()
578 __ Move(TMP, r2); in EmitSwap()
580 __ Move(r1, TMP); in EmitSwap()
594 __ Mfc1(TMP, f1); in EmitSwap()
598 __ Move(r2_l, TMP); in EmitSwap()
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| D | code_generator_mips64.cc | 492 ScratchRegisterScope ensure_scratch(this, TMP, V0, codegen_->GetNumberOfCoreRegisters()); in Exchange()
500 TMP, in Exchange()
507 __ StoreToOffset(store_type, TMP, SP, index1 + stack_offset); in Exchange()
767 gpr = TMP; in MoveLocation()
774 gpr = TMP; in MoveLocation()
784 __ LoadFromOffset(kLoadWord, TMP, SP, source.GetStackIndex()); in MoveLocation()
785 __ StoreToOffset(kStoreWord, TMP, SP, destination.GetStackIndex()); in MoveLocation()
787 __ LoadFromOffset(kLoadDoubleword, TMP, SP, source.GetStackIndex()); in MoveLocation()
788 __ StoreToOffset(kStoreDoubleword, TMP, SP, destination.GetStackIndex()); in MoveLocation()
811 __ Move(TMP, r2); in SwapLocations()
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| D | intrinsics_mips64.cc | 769 __ LoadConst64(TMP, kPrimLongMax); in GenRoundingMode()
770 __ Beqc(AT, TMP, &done); in GenRoundingMode()
948 __ Daddu(TMP, base, offset); in GenUnsafeGet()
954 __ Lw(trg, TMP, 0); in GenUnsafeGet()
958 __ Lwu(trg, TMP, 0); in GenUnsafeGet()
962 __ Ld(trg, TMP, 0); in GenUnsafeGet()
1050 __ Daddu(TMP, base, offset); in GenUnsafePut()
1057 __ Sw(value, TMP, 0); in GenUnsafePut()
1061 __ Sd(value, TMP, 0); in GenUnsafePut()
1232 __ Daddu(TMP, base, offset); in GenCas()
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| D | intrinsics_x86_64.cc | 1252 __ movl(CpuRegister(TMP), Address(temp1, component_offset)); in VisitSystemArrayCopy()
1253 __ testl(CpuRegister(TMP), CpuRegister(TMP)); in VisitSystemArrayCopy()
1255 __ MaybeUnpoisonHeapReference(CpuRegister(TMP)); in VisitSystemArrayCopy()
1256 __ cmpw(Address(CpuRegister(TMP), primitive_offset), Immediate(Primitive::kPrimNot)); in VisitSystemArrayCopy()
1263 __ movl(CpuRegister(TMP), Address(temp2, component_offset)); in VisitSystemArrayCopy()
1264 __ testl(CpuRegister(TMP), CpuRegister(TMP)); in VisitSystemArrayCopy()
1266 __ MaybeUnpoisonHeapReference(CpuRegister(TMP)); in VisitSystemArrayCopy()
1267 __ cmpw(Address(CpuRegister(TMP), primitive_offset), Immediate(Primitive::kPrimNot)); in VisitSystemArrayCopy()
1298 __ movl(CpuRegister(TMP), Address(temp1, component_offset)); in VisitSystemArrayCopy()
1299 __ testl(CpuRegister(TMP), CpuRegister(TMP)); in VisitSystemArrayCopy()
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| D | code_generator_x86_64.cc | 1033 blocked_core_registers_[TMP] = true; in SetupBlockedRegisters()
1179 __ movl(CpuRegister(TMP), Address(CpuRegister(RSP), source.GetStackIndex())); in Move()
1180 __ movl(Address(CpuRegister(RSP), destination.GetStackIndex()), CpuRegister(TMP)); in Move()
1202 __ movq(CpuRegister(TMP), Address(CpuRegister(RSP), source.GetStackIndex())); in Move()
1203 __ movq(Address(CpuRegister(RSP), destination.GetStackIndex()), CpuRegister(TMP)); in Move()
5130 __ movl(CpuRegister(TMP), Address(CpuRegister(RSP), source.GetStackIndex())); in EmitMove()
5131 __ movl(Address(CpuRegister(RSP), destination.GetStackIndex()), CpuRegister(TMP)); in EmitMove()
5142 __ movq(CpuRegister(TMP), Address(CpuRegister(RSP), source.GetStackIndex())); in EmitMove()
5143 __ movq(Address(CpuRegister(RSP), destination.GetStackIndex()), CpuRegister(TMP)); in EmitMove()
5204 __ movl(CpuRegister(TMP), Address(CpuRegister(RSP), mem)); in Exchange32()
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| D | code_generator_x86_64.h | 35 static constexpr Register TMP = R11; variable
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| /art/runtime/arch/mips/ |
| D | registers_mips.h | 63 TMP = T8, // scratch register (in addition to AT) enumerator
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| /art/runtime/arch/mips64/ |
| D | registers_mips64.h | 63 TMP = T8, // scratch register (in addition to AT) enumerator
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