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Searched refs:next_insn (Results 1 – 3 of 3) sorted by relevance

/art/compiler/linker/arm64/
Drelative_patcher_arm64.cc286 uint32_t next_insn = GetInsn(code, literal_offset + 4u); in NeedsErratum843419Thunk() local
293 if ((next_insn & 0xffc00000) == 0xb9400000 && in NeedsErratum843419Thunk()
294 (((next_insn >> 5) ^ adrp) & 0x1f) == 0) { in NeedsErratum843419Thunk()
302 if ((next_insn & 0x1f000000) == 0x11000000 && in NeedsErratum843419Thunk()
303 ((((next_insn >> 5) ^ adrp) & 0x1f) == 0 || ((next_insn ^ adrp) & 0x1f) != 0)) { in NeedsErratum843419Thunk()
308 if ((next_insn & 0xff000000) == 0x18000000) { in NeedsErratum843419Thunk()
313 if ((next_insn & 0xff000000) == 0x58000000) { in NeedsErratum843419Thunk()
314 bool is_aligned_load = (((next_offset >> 2) ^ (next_insn >> 5)) & 1) == 0; in NeedsErratum843419Thunk()
320 if ((next_insn & 0xbfc003e0) == 0xb94003e0) { in NeedsErratum843419Thunk()
/art/runtime/verifier/
Dmethod_verifier.h712 bool UpdateRegisters(uint32_t next_insn, RegisterLine* merge_line, bool update_merge_line)
Dmethod_verifier.cc4912 bool MethodVerifier::UpdateRegisters(uint32_t next_insn, RegisterLine* merge_line, in UpdateRegisters() argument
4915 RegisterLine* target_line = reg_table_.GetLine(next_insn); in UpdateRegisters()
4916 if (!GetInstructionFlags(next_insn).IsVisitedOrChanged()) { in UpdateRegisters()
4923 if (GetInstructionFlags(next_insn).IsReturn()) { in UpdateRegisters()
4929 const Instruction* ret_inst = Instruction::At(code_item_->insns_ + next_insn); in UpdateRegisters()
4944 << " to [" << reinterpret_cast<void*>(next_insn) << "]: " << "\n" in UpdateRegisters()
4954 GetInstructionFlags(next_insn).SetChanged(); in UpdateRegisters()