| /art/compiler/utils/arm/ |
| D | assembler_arm.h | 271 Address(Register rn, int32_t offset = 0, Mode am = Offset) : rn_(rn), rm_(R0), in rn_() argument
276 Address(Register rn, Register rm, Mode am = Offset) : rn_(rn), rm_(rm), offset_(0), in rn_() argument
281 Address(Register rn, Register rm, Shift shift, uint32_t count, Mode am = Offset) :
282 rn_(rn), rm_(rm), offset_(count), in rn_() argument
444 virtual void and_(Register rd, Register rn, const ShifterOperand& so,
447 virtual void ands(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) {
448 and_(rd, rn, so, cond, kCcSet);
451 virtual void eor(Register rd, Register rn, const ShifterOperand& so,
454 virtual void eors(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) {
455 eor(rd, rn, so, cond, kCcSet);
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| D | assembler_thumb2.h | 71 virtual void and_(Register rd, Register rn, const ShifterOperand& so,
74 virtual void eor(Register rd, Register rn, const ShifterOperand& so,
77 virtual void sub(Register rd, Register rn, const ShifterOperand& so,
80 virtual void rsb(Register rd, Register rn, const ShifterOperand& so,
83 virtual void add(Register rd, Register rn, const ShifterOperand& so,
86 virtual void adc(Register rd, Register rn, const ShifterOperand& so,
89 virtual void sbc(Register rd, Register rn, const ShifterOperand& so,
92 virtual void rsc(Register rd, Register rn, const ShifterOperand& so,
95 void tst(Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
97 void teq(Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
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| D | assembler_arm32.h | 41 virtual void and_(Register rd, Register rn, const ShifterOperand& so,
44 virtual void eor(Register rd, Register rn, const ShifterOperand& so,
47 virtual void sub(Register rd, Register rn, const ShifterOperand& so,
50 virtual void rsb(Register rd, Register rn, const ShifterOperand& so,
53 virtual void add(Register rd, Register rn, const ShifterOperand& so,
56 virtual void adc(Register rd, Register rn, const ShifterOperand& so,
59 virtual void sbc(Register rd, Register rn, const ShifterOperand& so,
62 virtual void rsc(Register rd, Register rn, const ShifterOperand& so,
65 void tst(Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
67 void teq(Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
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| D | assembler_arm32.cc | 57 Register rn ATTRIBUTE_UNUSED, in ShifterOperandCanHold()
65 void Arm32Assembler::and_(Register rd, Register rn, const ShifterOperand& so, in and_() argument
67 EmitType01(cond, so.type(), AND, set_cc, rn, rd, so); in and_()
71 void Arm32Assembler::eor(Register rd, Register rn, const ShifterOperand& so, in eor() argument
73 EmitType01(cond, so.type(), EOR, set_cc, rn, rd, so); in eor()
77 void Arm32Assembler::sub(Register rd, Register rn, const ShifterOperand& so, in sub() argument
79 EmitType01(cond, so.type(), SUB, set_cc, rn, rd, so); in sub()
82 void Arm32Assembler::rsb(Register rd, Register rn, const ShifterOperand& so, in rsb() argument
84 EmitType01(cond, so.type(), RSB, set_cc, rn, rd, so); in rsb()
87 void Arm32Assembler::add(Register rd, Register rn, const ShifterOperand& so, in add() argument
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| D | assembler_thumb2.cc | 361 inline int16_t Thumb2Assembler::CbxzEncoding16(Register rn, int32_t offset, Condition cond) { in CbxzEncoding16() argument
362 DCHECK(!IsHighRegister(rn)); in CbxzEncoding16()
366 return B15 | B13 | B12 | B8 | (cond == NE ? B11 : 0) | static_cast<int32_t>(rn) | in CbxzEncoding16()
371 inline int16_t Thumb2Assembler::CmpRnImm8Encoding16(Register rn, int32_t value) { in CmpRnImm8Encoding16() argument
372 DCHECK(!IsHighRegister(rn)); in CmpRnImm8Encoding16()
374 return B13 | B11 | (rn << 8) | value; in CmpRnImm8Encoding16()
418 inline int32_t Thumb2Assembler::LdrdEncoding32(Register rt, Register rt2, Register rn, int32_t offs… in LdrdEncoding32() argument
423 (static_cast<int32_t>(rn) << 16) | (static_cast<int32_t>(rt) << 12) | in LdrdEncoding32()
427 inline int32_t Thumb2Assembler::VldrsEncoding32(SRegister sd, Register rn, int32_t offset) { in VldrsEncoding32() argument
432 (static_cast<int32_t>(rn) << 16) | in VldrsEncoding32()
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| /art/disassembler/ |
| D | disassembler_arm.cc | 315 ArmRegister rn(instruction, 16); in DumpArm() local
316 if (rn.r == 0xf) { in DumpArm()
322 args << "[" << rn << ", #" << offset << "]"; in DumpArm()
324 args << "[" << rn << ", #" << offset << "]!"; in DumpArm()
326 args << "[" << rn << "], #" << offset; in DumpArm()
330 if (rn.r == 9) { in DumpArm()
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| /art/compiler/utils/arm64/ |
| D | assembler_arm64.cc | 81 void Arm64Assembler::AddConstant(XRegister rd, XRegister rn, int32_t value, in AddConstant() argument
85 ___ Add(reg_x(rd), reg_x(rn), value); in AddConstant()
90 temps.Exclude(reg_x(rd), reg_x(rn)); in AddConstant()
92 ___ Add(temp, reg_x(rn), value); in AddConstant()
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| D | assembler_arm64.h | 271 void AddConstant(XRegister rd, XRegister rn, int32_t value, vixl::Condition cond = vixl::al);
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