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Searched refs:ATOMIC_LOAD_NAND (Results 1 – 15 of 15) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h724 ATOMIC_LOAD_NAND, enumerator
DSelectionDAGNodes.h1204 N->getOpcode() == ISD::ATOMIC_LOAD_NAND ||
1323 N->getOpcode() == ISD::ATOMIC_LOAD_NAND ||
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp72 case ISD::ATOMIC_LOAD_NAND: return "AtomicLoadNand"; in getOperationName()
DLegalizeIntegerTypes.cpp142 case ISD::ATOMIC_LOAD_NAND: in PromoteIntegerResult()
1337 case ISD::ATOMIC_LOAD_NAND: in ExpandIntegerResult()
DSelectionDAG.cpp496 case ISD::ATOMIC_LOAD_NAND: in AddNodeIDCustom()
4895 Opcode == ISD::ATOMIC_LOAD_NAND || in getAtomic()
DLegalizeDAG.cpp3991 case ISD::ATOMIC_LOAD_NAND: in ConvertNodeToLibcall()
DSelectionDAGBuilder.cpp3516 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; in visitAtomicRMW()
/external/llvm/lib/Target/Mips/
DMips16ISelLowering.cpp141 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand); in Mips16TargetLowering()
/external/llvm/lib/Target/Sparc/
DSparcInstr64Bit.td532 defm ATOMIC_LOAD_NAND : AtomicRMW<atomic_load_nand_32, atomic_load_nand_64>;
/external/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp282 setTargetDAGCombine(ISD::ATOMIC_LOAD_NAND); in SITargetLowering()
2125 case ISD::ATOMIC_LOAD_NAND: in PerformDAGCombine()
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp682 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND) in getATOMIC()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td498 def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2,
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp212 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Custom); in SystemZTargetLowering()
4373 case ISD::ATOMIC_LOAD_NAND: in LowerOperation()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp866 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand); in ARMTargetLowering()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp20365 case ISD::ATOMIC_LOAD_NAND: in ReplaceNodeResults()