| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 185 BUILD_PAIR, enumerator
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 695 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in TryExpandADDWithMul()
703 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in TryExpandADDWithMul()
718 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in TryExpandADDWithMul()
762 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in ExpandADDSUB()
1809 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in PerformDAGCombine()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeFloatTypes.cpp | 72 case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break; in SoftenFloatResult()
140 return DAG.getNode(ISD::BUILD_PAIR, SDLoc(N), in SoftenFloatRes_BUILD_PAIR()
992 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; in ExpandFloatResult()
1426 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi); in ExpandFloatRes_XINT_TO_FP()
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| D | SelectionDAGDumper.cpp | 303 case ISD::BUILD_PAIR: return "build_pair"; in getOperationName()
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| D | LegalizeTypesGeneric.cpp | 144 Vals.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, in ExpandRes_BITCAST()
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| D | LegalizeIntegerTypes.cpp | 58 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; in PromoteIntegerResult()
881 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; in PromoteIntegerOperand()
1301 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; in ExpandIntegerResult()
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| D | SelectionDAGBuilder.cpp | 154 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); in getCopyFromParts()
185 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); in getCopyFromParts()
7507 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { in LowerArguments()
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| D | DAGCombiner.cpp | 1408 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); in visit()
7218 assert(N->getOpcode() == ISD::BUILD_PAIR); in CombineConsecutiveLoads()
7357 DAG.getNode(ISD::BUILD_PAIR, SDLoc(N0), VT, FlipBit, FlipBit); in visitBITCAST()
7429 DAG.getNode(ISD::BUILD_PAIR, SDLoc(N0), VT, FlipBit, FlipBit); in visitBITCAST()
7449 if (N0.getOpcode() == ISD::BUILD_PAIR) in visitBITCAST()
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| D | TargetLowering.cpp | 893 case ISD::BUILD_PAIR: { in SimplifyDemandedBits()
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| D | SelectionDAG.cpp | 704 case ISD::BUILD_PAIR: { in VerifySDNode()
3704 if (N1.getOpcode() == ISD::BUILD_PAIR) in getNode()
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| D | LegalizeDAG.cpp | 3682 case ISD::BUILD_PAIR: { in ExpandNode()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 1673 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(0), zero); in LowerUDIVREM64()
1674 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(1), zero); in LowerUDIVREM64()
1685 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, zero); in LowerUDIVREM64()
1715 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi); in LowerUDIVREM64()
2416 return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64, Zero, Lo); in performShlCombine()
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| D | AMDGPUISelDAGToDAG.cpp | 406 case ISD::BUILD_PAIR: { in Select()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 451 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments_32()
510 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments_32()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 4132 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0), in ExpandREAD_REGISTER()
4231 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); in ExpandBITCAST()
4604 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in Expand64BitShift()
6815 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Cycles32, in ReplaceREADCYCLECOUNTER()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1606 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 1307 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi); in extractLOHI()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 396 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); in PPCTargetLowering()
5152 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in LowerCall_64SVR4()
8073 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, in ReplaceNodeResults()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 13149 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps) in FP_TO_INTHelper()
17075 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops); in getReadPerformanceCounter()
17129 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops); in getReadTimeStampCounter()
20354 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF)); in ReplaceNodeResults()
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