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Searched refs:CR0 (Results 1 – 21 of 21) sorted by relevance

/external/clang/lib/Headers/
Dhtmintrin.h40 #define _HTM_STATE(CR0) ((CR0 >> 1) & 0x3) argument
/external/llvm/lib/Target/PowerPC/
DPPCInstrHTM.td89 // All HTM instructions, with the exception of tcheck, set CR0 with the
91 // instruction is executed. For tbegin., the EQ bit in CR0 can be used
DPPCInstrInfo.td760 let Defs = [CR0] in
775 let Defs = [CARRY, CR0] in
790 let Defs = [CARRY, CR0] in
804 let Defs = [CR0] in
818 let Defs = [CR0] in
834 let Defs = [CR0] in
850 let Defs = [CARRY, CR0] in
864 let Defs = [CR0] in
879 let Defs = [CARRY, CR0] in
893 let Defs = [CR0] in
[all …]
DPPCRegisterInfo.h30 Reg = PPC::CR0; in getCRFromCRBit()
DPPCRegisterInfo.td194 def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68, 68]>;
344 def CRRC : RegisterClass<"PPC", [i32], 32, (add CR0, CR1, CR5, CR6,
347 def CRRC0 : RegisterClass<"PPC", [i32], 32, (add CR0)>;
DPPCInstr64Bit.td208 let Defs = [CR0] in {
249 let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in
438 let Defs = [CR0] in {
636 let Defs = [CR0] in
645 let Defs = [CR0] in
936 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
945 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
968 Defs = [X0,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
977 Defs = [X0,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7]
DPPCRegisterInfo.cpp487 if (SrcReg != PPC::CR0) { in lowerCRSpilling()
532 if (DestReg != PPC::CR0) { in lowerCRRestore()
DPPCInstrInfo.cpp1631 Instr.modifiesRegister(PPC::CR0, TRI) || in optimizeCompareInstr()
1632 Instr.readsRegister(PPC::CR0, TRI))) in optimizeCompareInstr()
1737 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0); in optimizeCompareInstr()
DPPCISelLowering.cpp8195 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); in EmitAtomicBinary()
8325 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); in EmitPartwordAtomicBinary()
8907 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0) in EmitInstrWithCustomInserter()
8910 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); in EmitInstrWithCustomInserter()
8918 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); in EmitInstrWithCustomInserter()
9049 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0) in EmitInstrWithCustomInserter()
9052 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB); in EmitInstrWithCustomInserter()
9064 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB); in EmitInstrWithCustomInserter()
10981 R.first = PPC::CR0; in getRegForInlineAsmConstraint()
DPPCISelDAGToDAG.cpp2729 SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32); in Select()
/external/kernel-headers/original/uapi/asm-generic/
Dtermbits.h91 #define CR0 0000000 macro
/external/kernel-headers/original/uapi/asm-mips/asm/
Dtermbits.h111 #define CR0 0000000 macro
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCMCCodeEmitter.cpp336 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)); in get_crbitm_encoding()
350 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7); in getMachineOpValue()
/external/llvm/lib/IR/
DConstantRange.cpp140 [](const ConstantRange &CR0, const ConstantRange &CR1) { in makeNoWrapRegion() argument
141 return CR0.inverse().unionWith(CR1.inverse()).inverse(); in makeNoWrapRegion()
/external/llvm/lib/Target/PowerPC/InstPrinter/
DPPCInstPrinter.cpp358 case PPC::CR0: RegNo = 0; break; in printcrbitm()
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h355 ENTRY(CR0) \
/external/llvm/lib/Target/PowerPC/Disassembler/
DPPCDisassembler.cpp66 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
/external/llvm/lib/Target/X86/
DX86RegisterInfo.td284 def CR0 : X86Reg<"cr0", 0>;
/external/mesa3d/src/mesa/x86/
Dassyntax.h124 #define CR0 cr0 macro
186 #define CR0 %cr0 macro
/external/llvm/lib/Target/PowerPC/AsmParser/
DPPCAsmParser.cpp176 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
/external/llvm/docs/
DLangRef.rst3423 - ``y``: Condition register (``CR0-CR7``).