| /external/llvm/test/tools/llvm-objdump/ |
| D | win64-unwind-data.test | 15 OBJ-NEXT: Number of Codes: 8
18 OBJ-NEXT: Unwind Codes:
32 OBJ-NEXT: Number of Codes: 0
41 OBJ-NEXT: Number of Codes: 0
50 OBJ-NEXT: Number of Codes: 6
52 OBJ-NEXT: Unwind Codes:
64 EXE-NEXT: Number of Codes: 8
67 EXE-NEXT: Unwind Codes:
82 EXE-NEXT: Number of Codes: 0
92 EXE-NEXT: Number of Codes: 0
[all …]
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| /external/llvm/lib/IR/ |
| D | InlineAsm.cpp | 74 ConstraintCodeVector *pCodes = &Codes; in Parse()
80 pCodes = &multipleAlternatives[0].Codes; in Parse()
181 pCodes = &multipleAlternatives[multipleAlternativeIndex].Codes; in Parse()
206 Codes = scInfo.Codes; in selectAlternative()
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| /external/llvm/include/llvm/IR/ |
| D | InlineAsm.h | 109 ConstraintCodeVector Codes; member
149 ConstraintCodeVector Codes; member
|
| /external/pdfium/third_party/lcms2-2.6/src/ |
| D | cmscnvrt.c | 1073 …edIntentsTHR(cmsContext ContextID, cmsUInt32Number nMax, cmsUInt32Number* Codes, char** Descriptio… in cmsGetSupportedIntentsTHR() argument
1083 if (Codes != NULL) in cmsGetSupportedIntentsTHR()
1084 Codes[nIntents] = pt ->Intent; in cmsGetSupportedIntentsTHR()
1096 if (Codes != NULL) in cmsGetSupportedIntentsTHR()
1097 Codes[nIntents] = pt ->Intent; in cmsGetSupportedIntentsTHR()
1108 cmsUInt32Number CMSEXPORT cmsGetSupportedIntents(cmsUInt32Number nMax, cmsUInt32Number* Codes, char… in cmsGetSupportedIntents() argument
1110 return cmsGetSupportedIntentsTHR(NULL, nMax, Codes, Descriptions); in cmsGetSupportedIntents()
|
| /external/zxing/core/ |
| D | README.google | 12 QR Codes, Data Matrix, and the UPC family of 1D barcodes. It will provide
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 232 for (unsigned j = 0, je = C.Codes.size(); j < je; ++j) in mightUseCTR()
233 if (StringRef(C.Codes[j]).equals_lower("{ctr}")) in mightUseCTR()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 2528 rCodes = &info.Codes; in getMultipleConstraintMatchWeight()
2530 rCodes = &info.multipleAlternatives[maIndex].Codes; in getMultipleConstraintMatchWeight()
2616 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); in ChooseConstraint()
2622 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { in ChooseConstraint()
2624 TLI.getConstraintType(OpInfo.Codes[i]); in ChooseConstraint()
2631 assert(OpInfo.Codes[i].size() == 1 && in ChooseConstraint()
2634 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i], in ChooseConstraint()
2657 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; in ChooseConstraint()
2667 assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); in ComputeConstraintToUse()
2670 if (OpInfo.Codes.size() == 1) { in ComputeConstraintToUse()
[all …]
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| D | SelectionDAGBuilder.cpp | 6174 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { in visitInlineAsm()
6176 CType = TLI.getConstraintType(OpInfo.Codes[j]); in visitInlineAsm()
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| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 145 for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) { in hasInlineAsmMemConstraint()
146 TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]); in hasInlineAsmMemConstraint()
|
| /external/zlib/src/doc/ |
| D | rfc1951.txt | 437 values determined at step 2. Codes that are never used
661 Lit Value Bits Codes
705 Example: Codes 8, 16 (+2 bits 11),
850 Redundancy Codes", Proceedings of the Institute of Radio
|
| /external/pdfium/third_party/lcms2-2.6/include/ |
| D | lcms2.h | 1618 … CMSEXPORT cmsGetSupportedIntents(cmsUInt32Number nMax, cmsUInt32Number* Codes, char** Descriptio…
1619 …edIntentsTHR(cmsContext ContextID, cmsUInt32Number nMax, cmsUInt32Number* Codes, char** Descriptio…
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.td | 650 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
718 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
817 // Section B.27 - Trap on Integer Condition Codes Instruction
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 505 // Floating Point Branch Codes
|
| /external/tpm2/generator/ |
| D | raw_structures.txt | 159 TPM_CC (Command Codes) ............................................................................…
167 TPM_RC (Response Codes) ...........................................................................…
819 Table 12 — Format-Zero Response Codes .............................................................…
820 Table 13 — Format-One Response Codes ..............................................................…
1113 Figure 2 — Format-Zero Response Codes .............................................................…
1114 Figure 3 — Format-One Response Codes ..............................................................…
3228 TPM_CC (Command Codes)
4312 TPM_RC (Response Codes)
4425 Figure 2 — Format-Zero Response Codes
4441 Table 12 — Format-Zero Response Codes
[all …]
|
| D | raw_structures_fixed.txt | 159 TPM_CC (Command Codes) ............................................................................…
167 TPM_RC (Response Codes) ...........................................................................…
819 Table 12 — Format-Zero Response Codes .............................................................…
820 Table 13 — Format-One Response Codes ..............................................................…
1113 Figure 2 — Format-Zero Response Codes .............................................................…
1114 Figure 3 — Format-One Response Codes ..............................................................…
3219 TPM_CC (Command Codes)
4303 TPM_RC (Response Codes)
4416 Figure 2 — Format-Zero Response Codes
4432 Table 12 — Format-Zero Response Codes
[all …]
|
| D | raw_commands_fixed.txt | 188 Response Codes ....................................................................................…
601 Table 4 — Command-Independent Response Codes ......................................................…
1758 Response Codes
1786 Table 4 — Command-Independent Response Codes
|
| D | raw_commands.txt | 188 Response Codes ....................................................................................…
601 Table 4 — Command-Independent Response Codes ......................................................…
1758 Response Codes
1786 Table 4 — Command-Independent Response Codes
|
| /external/curl/docs/ |
| D | INTERNALS | 27 - [Return Codes and Informationals](#returncodes)
458 Return Codes and Informationals
|
| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 576 // Selection DAG Condition Codes
|
| /external/tcpdump/ |
| D | CHANGES | 21 Radius: update Packet Type Codes and Attribute Types with RFC/IANA names
|
| /external/libexif/po/ |
| D | de.po | 2536 "»R98« für ExifR98-Regeln. 4 Byte werden verwendet, inklusive des End-Codes "
3777 "Nullen aufgefüllt (00h). ID-Codes werden durch Registratur vergeben. Die "
3785 "dieses Feld ausliest, muss eine Funktion zum Ermitteln dieses Codes "
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| /external/avahi/specs/ |
| D | draft-cheshire-dnsext-multicastdns-04.txt | 2021 with non-zero Response Codes MUST be silently ignored.
|
| D | draft-cheshire-dnsext-multicastdns-03.txt | 2021 with non-zero Response Codes MUST be silently ignored.
|
| D | draft-cheshire-dnsext-multicastdns-05.txt | 2149 with non-zero Response Codes MUST be silently ignored.
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 27952 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && in ExpandInlineAsm()
27953 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { in ExpandInlineAsm()
|