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Searched refs:DL (Results 1 – 25 of 529) sorted by relevance

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/external/llvm/lib/Target/SystemZ/
DSystemZSelectionDAGInfo.cpp26 static SDValue emitMemMem(SelectionDAG &DAG, SDLoc DL, unsigned Sequence, in emitMemMem() argument
42 return DAG.getNode(Loop, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
43 DAG.getConstant(Size, DL, PtrVT), in emitMemMem()
44 DAG.getConstant(Size / 256, DL, PtrVT)); in emitMemMem()
45 return DAG.getNode(Sequence, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
46 DAG.getConstant(Size, DL, PtrVT)); in emitMemMem()
50 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain, in EmitTargetCodeForMemcpy() argument
59 return emitMemMem(DAG, DL, SystemZISD::MVC, SystemZISD::MVC_LOOP, in EmitTargetCodeForMemcpy()
67 static SDValue memsetStore(SelectionDAG &DAG, SDLoc DL, SDValue Chain, in memsetStore() argument
74 return DAG.getStore(Chain, DL, in memsetStore()
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DSystemZISelLowering.cpp458 EVT SystemZTargetLowering::getSetCCResultType(const DataLayout &DL, in getSetCCResultType() argument
511 bool SystemZTargetLowering::isLegalAddressingMode(const DataLayout &DL, in isLegalAddressingMode() argument
802 static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL, in convertLocVTToValVT() argument
808 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
811 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
815 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value); in convertLocVTToValVT()
817 Value = DAG.getLoad(VA.getValVT(), DL, Chain, Value, in convertLocVTToValVT()
824 Value = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i64, in convertLocVTToValVT()
826 Value = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Value); in convertLocVTToValVT()
835 static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL, in convertValVTToLocVT() argument
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/external/mesa3d/src/gallium/drivers/radeon/
DAMDGPUISelLowering.cpp53 DebugLoc DL, SelectionDAG &DAG, in LowerFormalArguments() argument
70 DebugLoc DL, SelectionDAG &DAG) const in LowerReturn() argument
72 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain); in LowerReturn()
105 DebugLoc DL = Op.getDebugLoc(); in LowerINTRINSIC_WO_CHAIN() local
113 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
115 return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
119 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
121 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
124 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
127 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
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DAMDILISelLowering.cpp361 DebugLoc DL = Op.getDebugLoc(); in LowerBUILD_VECTOR() local
363 DL, in LowerBUILD_VECTOR()
386 DL, in LowerBUILD_VECTOR()
397 DL, in LowerBUILD_VECTOR()
408 DL, in LowerBUILD_VECTOR()
424 DebugLoc DL = Op.getDebugLoc(); in LowerSIGN_EXTEND_INREG() local
434 Data = DAG.getNode(ISD::ZERO_EXTEND, DL, IVT, Data); in LowerSIGN_EXTEND_INREG()
440 Data = DAG.getNode(ISD::SHL, DL, DVT, Data, Shift); in LowerSIGN_EXTEND_INREG()
442 Data = DAG.getNode(ISD::SRA, DL, DVT, Data, Shift); in LowerSIGN_EXTEND_INREG()
446 Data = DAG.getSExtOrTrunc(Data, DL, Op.getOperand(0).getValueType()); in LowerSIGN_EXTEND_INREG()
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/external/llvm/lib/IR/
DMangler.cpp34 const DataLayout &DL, char Prefix) { in getNameWithPrefixImpl() argument
47 OS << DL.getPrivateGlobalPrefix(); in getNameWithPrefixImpl()
49 OS << DL.getLinkerPrivateGlobalPrefix(); in getNameWithPrefixImpl()
59 const DataLayout &DL, in getNameWithPrefixImpl() argument
61 char Prefix = DL.getGlobalPrefix(); in getNameWithPrefixImpl()
62 return getNameWithPrefixImpl(OS, GVName, PrefixTy, DL, Prefix); in getNameWithPrefixImpl()
66 const DataLayout &DL) { in getNameWithPrefix() argument
67 return getNameWithPrefixImpl(OS, GVName, DL, Default); in getNameWithPrefix()
71 const Twine &GVName, const DataLayout &DL) { in getNameWithPrefix() argument
73 char Prefix = DL.getGlobalPrefix(); in getNameWithPrefix()
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/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp625 SDLoc DL(Op); in LowerOperation() local
631 DAG.getConstant(0, DL, MVT::i32), // SWZ_X in LowerOperation()
632 DAG.getConstant(1, DL, MVT::i32), // SWZ_Y in LowerOperation()
633 DAG.getConstant(2, DL, MVT::i32), // SWZ_Z in LowerOperation()
634 DAG.getConstant(3, DL, MVT::i32) // SWZ_W in LowerOperation()
636 return DAG.getNode(AMDGPUISD::EXPORT, DL, Op.getValueType(), Args); in LowerOperation()
649 SDLoc DL(Op); in LowerOperation() local
669 interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL, in LowerOperation()
670 MVT::v4f32, DAG.getTargetConstant(slot / 4, DL, MVT::i32)); in LowerOperation()
673 DL, MVT::f32, SDValue(interp, 0)); in LowerOperation()
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DAMDGPUISelLowering.cpp574 SDLoc DL, SelectionDAG &DAG) const { in LowerReturn() argument
575 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain); in LowerReturn()
692 SDLoc DL(InitPtr); in LowerConstantInitializer() local
698 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, DL, VT), InitPtr, in LowerConstantInitializer()
706 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, DL, VT), InitPtr, in LowerConstantInitializer()
718 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), DL, PtrVT); in LowerConstantInitializer()
719 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset); in LowerConstantInitializer()
725 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); in LowerConstantInitializer()
742 SDValue Offset = DAG.getConstant(i * EltSize, DL, PtrVT); in LowerConstantInitializer()
743 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset); in LowerConstantInitializer()
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DSILowerControlFlow.cpp145 DebugLoc DL = From.getDebugLoc(); in Skip() local
146 BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ)) in Skip()
153 DebugLoc DL = MI.getDebugLoc(); in SkipIfDead() local
164 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ)) in SkipIfDead()
168 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP)) in SkipIfDead()
180 BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM)); in SkipIfDead()
185 DebugLoc DL = MI.getDebugLoc(); in If() local
189 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg) in If()
192 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg) in If()
203 DebugLoc DL = MI.getDebugLoc(); in Else() local
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DAMDGPUISelDAGToDAG.cpp142 SDNode *getS_BFE(unsigned Opcode, SDLoc DL, SDValue Val,
358 SDLoc DL(N); in Select() local
359 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in Select()
373 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in Select()
384 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL, in Select()
393 DL, EltVT); in Select()
397 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL, MVT::i32); in Select()
411 SDLoc DL(N); in Select() local
413 RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32); in Select()
414 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32); in Select()
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/external/llvm/bindings/ocaml/target/
Dtarget_ocaml.c69 value DL) { in llvm_datalayout_add_to_pass_manager() argument
70 LLVMAddTargetData(DataLayout_val(DL), PM); in llvm_datalayout_add_to_pass_manager()
75 CAMLprim value llvm_datalayout_byte_order(value DL) { in llvm_datalayout_byte_order() argument
76 return Val_int(LLVMByteOrder(DataLayout_val(DL))); in llvm_datalayout_byte_order()
80 CAMLprim value llvm_datalayout_pointer_size(value DL) { in llvm_datalayout_pointer_size() argument
81 return Val_int(LLVMPointerSize(DataLayout_val(DL))); in llvm_datalayout_pointer_size()
85 CAMLprim LLVMTypeRef llvm_datalayout_intptr_type(LLVMContextRef C, value DL) { in llvm_datalayout_intptr_type() argument
86 return LLVMIntPtrTypeInContext(C, DataLayout_val(DL));; in llvm_datalayout_intptr_type()
90 CAMLprim value llvm_datalayout_qualified_pointer_size(value AS, value DL) { in llvm_datalayout_qualified_pointer_size() argument
91 return Val_int(LLVMPointerSizeForAS(DataLayout_val(DL), Int_val(AS))); in llvm_datalayout_qualified_pointer_size()
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/external/llvm/include/llvm/Analysis/
DInstructionSimplify.h52 const DataLayout &DL,
61 const DataLayout &DL,
70 const DataLayout &DL,
79 const DataLayout &DL,
88 const DataLayout &DL,
96 Value *SimplifyMulInst(Value *LHS, Value *RHS, const DataLayout &DL,
104 Value *SimplifySDivInst(Value *LHS, Value *RHS, const DataLayout &DL,
112 Value *SimplifyUDivInst(Value *LHS, Value *RHS, const DataLayout &DL,
121 const DataLayout &DL,
129 Value *SimplifySRemInst(Value *LHS, Value *RHS, const DataLayout &DL,
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DValueTracking.h46 const DataLayout &DL, unsigned Depth = 0,
56 bool haveNoCommonBitsSet(Value *LHS, Value *RHS, const DataLayout &DL,
64 const DataLayout &DL, unsigned Depth = 0,
74 bool isKnownToBeAPowerOfTwo(Value *V, const DataLayout &DL,
84 bool isKnownNonZero(Value *V, const DataLayout &DL, unsigned Depth = 0,
90 bool isKnownNonNegative(Value *V, const DataLayout &DL, unsigned Depth = 0,
97 bool isKnownNonEqual(Value *V1, Value *V2, const DataLayout &DL,
111 bool MaskedValueIsZero(Value *V, const APInt &Mask, const DataLayout &DL,
124 unsigned ComputeNumSignBits(Value *Op, const DataLayout &DL,
169 const DataLayout &DL);
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/external/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp270 bool WebAssemblyTargetLowering::isLegalAddressingMode(const DataLayout &DL, in isLegalAddressingMode() argument
296 static void fail(SDLoc DL, SelectionDAG &DAG, const char *msg) { in fail() argument
299 DiagnosticInfoUnsupported(DL, *MF.getFunction(), msg, SDValue())); in fail()
319 SDLoc DL = CLI.DL; in LowerCall() local
326 fail(DL, DAG, in LowerCall()
330 fail(DL, DAG, "WebAssembly doesn't support patch point yet"); in LowerCall()
337 fail(DL, DAG, "WebAssembly doesn't support tail call yet"); in LowerCall()
344 fail(DL, DAG, "WebAssembly doesn't support more than 1 returned value yet"); in LowerCall()
349 fail(DL, DAG, "WebAssembly hasn't implemented byval arguments"); in LowerCall()
351 fail(DL, DAG, "WebAssembly hasn't implemented nest arguments"); in LowerCall()
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DWebAssemblyFrameLowering.cpp72 const DebugLoc& DL) { in adjustStackPointer() argument
76 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), SPReg) in adjustStackPointer()
84 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::LOAD_I32), SPReg) in adjustStackPointer()
90 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg) in adjustStackPointer()
92 BuildMI(MBB, InsertPt, DL, in adjustStackPointer()
98 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg) in adjustStackPointer()
102 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::STORE_I32), WebAssembly::SP32) in adjustStackPointer()
114 DebugLoc DL = I->getDebugLoc(); in eliminateCallFramePseudoInstr() local
120 TII, I, DL); in eliminateCallFramePseudoInstr()
138 DebugLoc DL; in emitPrologue() local
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/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp481 SDLoc DL(N); in performDivRemCombine() local
483 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, in performDivRemCombine()
490 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, in performDivRemCombine()
499 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, in performDivRemCombine()
559 SDLoc DL(Op); in createFPCmp() local
565 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, in createFPCmp()
566 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); in createFPCmp()
571 SDValue False, SDLoc DL) { in createCMovFP() argument
576 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, in createCMovFP()
610 const SDLoc DL(N); in performSELECTCombine() local
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DMipsSEISelLowering.cpp428 SDLoc DL(ADDENode); in selectMADD() local
431 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped, in selectMADD()
438 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped, in selectMADD()
445 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); in selectMADD()
449 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); in selectMADD()
500 SDLoc DL(SUBENode); in selectMSUB() local
503 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped, in selectMSUB()
510 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue, in selectMSUB()
517 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub); in selectMSUB()
521 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MSub); in selectMSUB()
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DMipsLongBranch.cpp80 void replaceBranch(MachineBasicBlock &MBB, Iter Br, DebugLoc DL,
216 DebugLoc DL, MachineBasicBlock *MBBOpnd) { in replaceBranch() argument
222 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc); in replaceBranch()
255 DebugLoc DL = I.Br->getDebugLoc(); in expandToLongBranch() local
295 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
297 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) in expandToLongBranch()
316 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT) in expandToLongBranch()
319 .append(BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB)) in expandToLongBranch()
320 .append(BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT) in expandToLongBranch()
327 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT) in expandToLongBranch()
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/external/llvm/lib/Analysis/
DValueTracking.cpp75 static unsigned getBitWidth(Type *Ty, const DataLayout &DL) { in getBitWidth() argument
79 return DL.getPointerTypeSizeInBits(Ty); in getBitWidth()
131 const DataLayout &DL, unsigned Depth,
135 const DataLayout &DL, unsigned Depth, in computeKnownBits() argument
138 ::computeKnownBits(V, KnownZero, KnownOne, DL, Depth, in computeKnownBits()
142 bool llvm::haveNoCommonBitsSet(Value *LHS, Value *RHS, const DataLayout &DL, in haveNoCommonBitsSet() argument
152 computeKnownBits(LHS, LHSKnownZero, LHSKnownOne, DL, 0, AC, CxtI, DT); in haveNoCommonBitsSet()
153 computeKnownBits(RHS, RHSKnownZero, RHSKnownOne, DL, 0, AC, CxtI, DT); in haveNoCommonBitsSet()
158 const DataLayout &DL, unsigned Depth,
162 const DataLayout &DL, unsigned Depth, in ComputeSignBit() argument
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DConstantFolding.cpp53 static Constant *FoldBitCast(Constant *C, Type *DestTy, const DataLayout &DL) { in FoldBitCast() argument
86 unsigned BitShift = DL.getTypeAllocSizeInBits(SrcEltTy); in FoldBitCast()
90 if (DL.isLittleEndian()) in FoldBitCast()
108 return FoldBitCast(ConstantVector::get(Ops), DestTy, DL); in FoldBitCast()
140 C = FoldBitCast(C, DestIVTy, DL); in FoldBitCast()
164 bool isLittleEndian = DL.isLittleEndian(); in FoldBitCast()
200 unsigned DstBitSize = DL.getTypeSizeInBits(DstEltTy); in FoldBitCast()
237 APInt &Offset, const DataLayout &DL) { in IsConstantOffsetFromGlobal() argument
240 unsigned BitWidth = DL.getPointerTypeSizeInBits(GV->getType()); in IsConstantOffsetFromGlobal()
252 return IsConstantOffsetFromGlobal(CE->getOperand(0), GV, Offset, DL); in IsConstantOffsetFromGlobal()
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/external/llvm/lib/Target/X86/
DX86FrameLowering.cpp255 DebugLoc DL = MBB.findDebugLoc(MBBI); in emitSPUpdate() local
270 BuildMI(MBB, MBBI, DL, TII.get(Opc), Reg) in emitSPUpdate()
275 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) in emitSPUpdate()
294 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc)) in emitSPUpdate()
306 MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue); in emitSPUpdate()
317 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL, in BuildStackAdjustment() argument
347 MI = addRegOffset(BuildMI(MBB, MBBI, DL, in BuildStackAdjustment()
356 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) in BuildStackAdjustment()
396 MachineBasicBlock::iterator MBBI, DebugLoc DL, in BuildCFI() argument
400 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in BuildCFI()
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/external/llvm/test/Bindings/OCaml/
Dtarget.ml43 let module DL = DataLayout in
45 let dl = DL.of_string layout in
48 assert_equal (DL.as_string dl) layout;
49 assert_equal (DL.byte_order dl) Endian.Little;
50 assert_equal (DL.pointer_size dl) 4;
51 assert_equal (DL.intptr_type context dl) i32_type;
52 assert_equal (DL.qualified_pointer_size 0 dl) 4;
53 assert_equal (DL.qualified_intptr_type context 0 dl) i32_type;
54 assert_equal (DL.size_in_bits sty dl) (Int64.of_int 96);
55 assert_equal (DL.store_size sty dl) (Int64.of_int 12);
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/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp190 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, in LowerFormalArguments() argument
221 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerFormalArguments()
227 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
230 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
234 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); in LowerFormalArguments()
239 DiagnosticInfoUnsupported Err(DL, *MF.getFunction(), in LowerFormalArguments()
247 DL, *MF.getFunction(), in LowerFormalArguments()
288 DiagnosticInfoUnsupported Err(CLI.DL, *MF.getFunction(), in LowerCall()
298 DiagnosticInfoUnsupported Err(CLI.DL, *MF.getFunction(), in LowerCall()
305 Chain, DAG.getConstant(NumBytes, CLI.DL, PtrVT, true), CLI.DL); in LowerCall()
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/external/llvm/lib/Transforms/ObjCARC/
DProvenanceAnalysis.cpp35 const DataLayout &DL = A->getModule()->getDataLayout(); in relatedSelect() local
40 return related(A->getTrueValue(), SB->getTrueValue(), DL) || in relatedSelect()
41 related(A->getFalseValue(), SB->getFalseValue(), DL); in relatedSelect()
44 return related(A->getTrueValue(), B, DL) || in relatedSelect()
45 related(A->getFalseValue(), B, DL); in relatedSelect()
50 const DataLayout &DL = A->getModule()->getDataLayout(); in relatedPHI() local
58 PNB->getIncomingValueForBlock(A->getIncomingBlock(i)), DL)) in relatedPHI()
66 if (UniqueSrc.insert(PV1).second && related(PV1, B, DL)) in relatedPHI()
108 const DataLayout &DL) { in relatedCheck() argument
110 A = GetUnderlyingObjCPtr(A, DL); in relatedCheck()
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/external/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h234 DebugLoc DL, in BuildMI() argument
236 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL)); in BuildMI()
242 DebugLoc DL, in BuildMI() argument
245 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL)) in BuildMI()
254 DebugLoc DL, in BuildMI() argument
258 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); in BuildMI()
265 DebugLoc DL, in BuildMI() argument
269 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); in BuildMI()
276 DebugLoc DL, in BuildMI() argument
281 return BuildMI(BB, MII, DL, MCID, DestReg); in BuildMI()
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/external/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp71 DebugLoc DL,
77 DebugLoc DL,
83 DebugLoc DL,
88 DebugLoc DL,
93 DebugLoc DL, unsigned DReg, unsigned Lane,
98 DebugLoc DL);
432 DebugLoc DL, in createDupLane() argument
438 DL, in createDupLane()
451 DebugLoc DL, in createExtractSubreg() argument
457 DL, in createExtractSubreg()
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